International Business Machines Corporation

Dudley A Chance

David B Goland

Chung W Ho

Ho-Ming Tong

Sudipta Kumar Ray

Timothy C Reiley

Christopher H Bajorek

Timothy Rea Dinger

David P Lapotin

Michael Sampogna

Gareth Geoffrey Hougham

Subhash Laxman Shinde

Srinivasa S Reddy

Donald Rene Wall

David A Thompson

Gerard Vincent Kopcsay

Nicholas G Koopman

Evan Ezra Davidson

Yung-Haw Hu

Somnath Bhattacharya

Alan Platt

Walter V Vilkelis

Methods of fabricating powders of electrically conductive particles supersaturated with grain growth control additives are described. A molten admixture of an electrically conductive material and a grain growth control additive is atomized by spraying an inert atmosphere forming fine molten particles which rapidly cool to form solid particles which are supersaturated with the grain growth control additive. The supersaturated particles are heated to form an electrical conductor having grain sizes less than about 25 microns. The supersaturated particles can be combined with a binder to form an electrical conductor forming paste. Patterns of the paste can be embedded in a green ceramic which can be sintered to form a semiconductor chip packaging substrate having electrical conductors with controlled grain size. During sintering of the combination of ceramic precursor and conductor forming paste, the grain growth control additive results in a substantially void free and crack free via filled with metal having a fine grain morphology.

Supersaturation method for producing metal powder with a uniform

A hermetic package for an electronic device is manufactured by providing a green glass ceramic body with a green via to produce a workpiece. The workpiece is sintered at a temperature at or above 500.degree. C., while compressing the workpiece at a pressure at or above 100 pounds per square inch, so as to obtain a hermetic package. The green via comprises a mixture of copper and a glass ceramic material with a sufficient volume of glass to produce a hermetic package, yet with sufficient copper to have a suitable electrical conductivity. The hermetic package thus produced comprises a sintered glass ceramic body having an electrically conductive sintered via which is hermetically bonded to the glass ceramic body and which comprises a mixture of an electrically conductive material and a glass ceramic material. The electrically conductive material forms at most 50 volume percent of the via. The workpiece may be sintered in a sintering fixture having a frame and a compensating insert. The compensating insert and frame bound a sintering chamber for accommodating the workpiece. By providing a frame having a thermal expansion coefficient greater than that of the workpiece, and by providing a compensating insert having a thermal expansion coefficient greater than that of the frame, a close fit can be assured between the workpiece and the sintering fixture over a large range of temperatures.

Hermetic package for an electronic device

Hermetic package for an electronic device and method of manufacturing

A semiconductor package is described for supporting and interconnecting semiconductor chips, each chip having contact lands on a contact surface, the package also including a substrate with a contact surface. An interposer module is disposed between at least one chip's contact surface and the substrate's contact surface. The interposer module has first and second opposed surfaces and a first plurality of contact locations positioned on its first surface which mate with a chip's contact land. A second plurality of contact locations on the interposer modules second surface are positioned to mate with contact lands on the substrate. A set of conductive vias are positioned within the interposer module and connect the first plurality of contact locations with a first subset of the second plurality of contact locations. A distributed capacitance layer is positioned within the interposer and is adjacent to its first surface. Adjacent to the second surface are X and Y lines which can be used to make engineering change interconnections.

Semiconductor chip interposer module with engineering change wiring and

A hermetic package for an electronic device is manufactured by providing a green glass ceramic body with a green via to produce a workpiece. The workpiece is sintered at a temperature at or above 500.degree. C., while compressing the workpiece at a pressure at or above 100 pounds per square inch, so as to obtain a hermetic package. The green via comprises a mixture of copper and a glass ceramic material with a sufficient volume of glass to produce a hermetic package, yet with sufficient copper to have a suitable electrical conductivity. The hermetic package thus produced comprises a sintered glass ceramic body having an electrically conductive sintered via which is hermetically bonded to the glass ceramic body and which comprises a mixture of an electrically conductive material and a glass ceramic material. The electrically conductive material forms at most 50 volume percent of the via. The workpeice may be sintered in a sintering fixture having a frame and a compensating insert. The compensating insert and frame bound a sintering chamber for accommodating the workpiece. By providing a frame having a thermal expansion coefficient greater than that of the workpiece, and by providing a compensating insert having a thermal expansion coefficient greater than that of the frame, a close fit can be assured between the workpiece and the sintering fixture over a large range of temperatures.

Electrical impedance matching for through plane connections or vias in a multiplane laminated wiring structure is provided by arranging the vias in patterns conforming to a standard characteristic impedance configuration. The pattern may be a five wire configuration with four vias surrounding the fifth and repeated over the area of the plane.

Matched impedance vertical conductors in multilevel dielectric laminated

An integrated circuit carrier comprising a modular substrate having an upper surface, a multitude of electrically conducting device terminals on the upper surface of the substrate, a multitude of electrically conducting engineering change pads also on the upper surface of the substrate, and an engineering change network to form a unique electrical connection between each of an arbitrary subset of the device terminals and each of an arbitrary subset of the engineering change pads. The engineering change network includes a multitude of connecting pads, and a multitude of first, second, and third conductive leads or wires, and each of the connecting pads includes first and second spaced apart sections.

Integrated circuit carriers and a method for making engineering changes

Ceramic substrates and a method for forming the ceramic substrates containing multi-level and interconnected circuit patterns of copper based conductors which are resistant to oxidation, said formation includes burn-out of binders in air. The oxidation resistant copper based conductors are composed primarily of copper and additives such as zinc, platinum and chrome.

Method for producing multi-layer ceramic substrates with oxidation

A high dielectric constant glass-ceramic material comprising small conducting grains based on BaTiO.sub.3 and/or SrTiO.sub.3 on the order of about 0.5-10.0 .mu.m surrounded by a thin microcrystalline insulating barrier layer at the grain boundary about 0.01-0.10 .mu.m thick wherein the conductivity of the grains is enhanced by addition of about 0.1-4.0 mol % of a dopant selected from among Group V elements, Ge and Si substantially incorporated in the bulk lattice of the grains upon Ti sites. A novel process for forming the glass-ceramic material is also disclosed.

Doped titanate glass-ceramic for grain boundary barrier layer capacitors

A method for forming a pattern in a metallic and/or ceramic substrate by laminating together the substrate which is in the green stage and a composite of a photosensitive material and a backing wherein the photosensitive material has been developed into the desired pattern, and then subjecting the substrate to elevated temperatures in order to cause sintering of the substrate and removal of the photosensitive material, thereby resulting in embedding of the pattern into the sintered substrate.

Forming patterns in metallic or ceramic substrates

An electrolytic print head comprises a plurality of styli (16, 18) between electrically insulative laminae (38, 42, 48, 38', 42', 48') which space the styli from planar reference electrodes (20, 22, 24). The styli and reference electrodes are fabricated of a mixture of ruthenium dioxide and corrosion resistant glass, and the insulative laminae are fabricated of corrosion resistant glass. The method of manufacture of the print head facilitates use of styli and reference electrodes requiring high temperature processing prior to deposition of metal conductor tracks for the styli and reference electrodes.

Electrolytic printing head

A chip carrying module includes a number of engineering change lines buried below the surface of the module. The engineering change lines are interrupted periodically to provide a set of vias extending up to the upper surface of the module between each set of chips where the vias are connected by dumbbell-shaped pads including a narrow link which permits laser deletion or the like. In addition, the dumbbell-shaped pads are located adjacent to the fan-out pads for the chips. Thus, the fan-out pads can be connected to the dumbbell-shaped pads by means of fly-wires. In addition, individual engineering change lines can be connected together to reach every region of the module by connecting a fly-wire from one dumbbell-shaped pad to another. In addition, by deleting the links at such dumbbell-shaped pads, the engineering change connections are limited to the particular path required.

Chip carrier with embedded engineering change lines with severable

The top surface metallurgy of LSI chip carriers is improved by multiple and phased interface of metal layers which enable such metallurgies to be suitable for joining by solder reflow and wire bonding techniques. The modifications result in separating the solder bonding metallurgy from the fan-out conductor metallurgy with an intermediate layer of a metal such as Cr or Ti which prevents the formation of intermetallic alloys which are mechanically weak or brittle and tend to fracture because of thermal fatigue stresses caused by thermal cycling during either multiple (up to 50) solder bonding reflow operations or operation of the circuit. The fan-out metallurgy conductors are preferably composed of Cr-Cu-Cr layers covered by at least one upper metal layer which is separated from the Cu of the conductor by means of a metal such as phased layers of Cr or Ti deposited before the other upper metal layer or layers. Solder ball bonding surfaces are composed of additional metal in the form of Au, Cu and Ni. The solderless bonding surfaces are composed of a metal selected from Au, Cr, Ti, Al and Co.

Layered metal film structures for LSI chip carriers adapted for solder

A carrier for LSI chips includes a built-in capacitor structure in the carrier. The capacitor is located beneath the chip with the plates of the capacitor parallel to the chip mounting surface or at right angles to the chip mounting surface. The capacitor is formed by assembling an array of capacitive segments together to form the first one of the plates of a capacitor with the other plate spanning a plurality of the segments of the first plate. Each of the segments of the first plate includes a set of conductive via lines which extend up to a severable link on the chip mounting surface. The severable via is cut by means of a laser beam or the like when the capacitor must be repaired by deleting a defective segment of the capacitor. Preferably, the structure includes a pair of parallel conductive charge redistribution planes above and below the capacitor plates with connections to the respective plates providing a low inductance structure achieved by providing a current distribution which results in cancellation of magnetic flux. The lower redistribution plane is preferably connected directly to the lower capacitor plate. The upper redistribution plane is preferably connected to the segments of the first capacitor plate by means of the vias which extend first to the chip mounting surface and then down to the redistribution plane which has connections to the chip mounting pads.

LSI Chip carrier with buried repairable capacitor with low inductance

A laminated capacitor is joined to the surface of a chip carrier for large scale integrated circuit chips. The capacitor lies adjacent to positions where chips are located. The capacitor includes a plurality of capacitor plates. The capacitor is bonded to the chip carrier with an array of solder bars comprising an elongated strip of metallic material. Each of the bars is connected to a set of the capacitor plates in the laminated capacitor by means of tab connections on the plates, whereby each of the plates is connected by a plurality of tabs to a plurality of the solder bars. Methods of fabrication of the laminated capacitor structure and solder bars are described.

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Danbury, CT, United States of America

Dudley A Chance