Samsung Electronics Co., Ltd.

Duck Hyun Chang

Joo Young Hwang

Song Ho Yoon

Jeong Hur

Young-Gyu Kang

Nyun-Tae Kim

Soon-Bok Jang

Shu-Jiang Wang

Dae-Seung Jeong

Ki-Mio Ueda

Hwa-Su Koh

Nyun Tae Kim

Hwa Su Koh

Ki Mio Ueda

Jae Gyu Lee

Dae Seung Jeong

A method of operating a universal flash storage (UFS) device communicating with a UFS host via a link is provided. The method determines in the UFS device whether a warm reset of the link is necessary while the UFS device is communicating with the UFS host via the link. Upon determining that the warm reset of the link is necessary, the UFS device initiates the warm reset of the link.

Method operating universal flash storage (UFS) device, method operating UFS host, and method operating system including both

The phase detection circuit may allow an operating speed of a semiconductor circuit to be increased irrespective of whether a combinational logic circuit within the semiconductor circuit operates at lower operating speeds. The phase detection circuit may adjust a data rate of an input data signal and selectively enable reference signals and error signals. The phase detection circuit may be included within a clock data recovery circuit.

Phase detection circuit and method thereof and clock recovery circuit and method thereof

A recovery circuit may include a phase detector, a quadrant decision unit, a quadrant controller, a charge pump unit, and a phase interpolator. The phase detector may compare a phase of input data with a phase of a current output clock to generate first up signal and first down signal and the quadrant decision unit may determine the phase location for the current output clock and output quadrant decision signals based on a phase location. The quadrant controller may output a second up signal and a second down signal based on the first up signal and the first down signal and the quadrant decision signals, and the charge pump unit may output a first and second phase control voltage based on the second up signal and the second down signal. The phase interpolator may select clocks from a plurality of clocks based on the quadrant decision signals and output an output clock signal based on the selected clocks.

Recovery circuits and methods for the same

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Seongnam-si, South Korea

Duck Hyun Chang