Fairchild Semiconductor Corporation

Duc Q Chau

Dean E Probst

Steven Paul Sapp

Izak Bencuya

Brian Sze-Ki Mo

Brian S Mo

Bruce Douglas Marchant

James J Murphy

Robert Herrick

Becky Losee

Teina L Pardue

A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.

Method of manufacture and structure for a trench transistor having a heavy body region

Method of manufacturing a trench transistor having a heavy body region

Field effect transistor and method of its manufacture

Self-aligned trench MOSFETs and methods for manufacturing the same are disclosed. By having a self-aligned structure, the number of MOSFETS per unit area&#x2014;the cell density&#x2014;is increased, making the MOSFETs cheaper to produce. The self-aligned structure for the MOSFET is provided by making the sidewall of the overlying isolation dielectric layer substantially aligned with the sidewall of the gate conductor. Such an alignment can be made through any number of methods such as using a dual dielectric process, using a selective dielectric oxidation process, using a selective dielectric deposition process, or a spin-on-glass dielectric process.

Self-aligned trench MOSFETs and methods for making the same

A trench transistor with lower leakage current and higher gate rupture voltage. The gate oxide layer of a trench transistor is grown at a temperature above about 1100&#xb0; C. to reduce thinning of the oxide layer at the corners of the trench. In a further embodiment, a conformal layer of silicon nitride is deposited over the high-temperature oxide layer, and a second oxide layer is formed between the silicon nitride layer and the gate polysilicon. The first gate oxide layer, silicon nitride layer, and second oxide layer form a composite gate dielectric structure that substantially reduces leakage current in trench field effect transistors.

Method of forming a trench transistor having a superior gate dielectric

A double-diffused metal-oxide-semiconductor (&ldquo;DMOS&rdquo;) field-effect transistor ( ) with a metal gate ( ). A sacrificial gate layer is patterned to provide a self-aligned source mask. The source regions ( ) are thus aligned to the gate ( ), and the source diffusion provides a slight overlap ( ) for good turn-on characteristics and low leakage. The sacrificial gate layer is capable of withstanding the diffusion temperatures of the DMOS process and is selectively etchable. After the high-temperature processing is completed, the sacrificial gate layer is stripped and a metal gate layer is formed over the substrate, filling the volume left by the stripped sacrificial gate material. In one embodiment, a chemical-mechanical polishing technique is used to planarize the metal gate layer.

Metal gate double diffusion MOSFET with improved switching speed and reduced gate tunnel leakage

A trench transistor with lower leakage current and higher gate rupture voltage. The gate oxide layer of a trench transistor is grown at a temperature above about 1100&deg; C. to reduce thinning of the oxide layer at the corners of the trench. In a further embodiment, a conformal layer of silicon nitride is deposited over the high-temperature oxide layer, and a second oxide layer is formed between the silicon nitride layer and the gate polysilicon. The first gate oxide layer, silicon nitride layer, and second oxide layer form a composite gate dielectric structure that substantially reduces leakage current in trench field effect transistors.

Trench transistor with superior gate dielectric

A process for forming a trench in a semiconductor material is provided. The process includes (a) providing a semiconductor substrate, a first mask layer adjacent the surface of the semiconductor substrate, and a second mask layer adjacent the surface of the first mask layer, the second mask layer defining a first open area and the first mask layer defining a second open area that is larger than the first open area and aligned therewith in a manner so that in the area of the openings the first mask layer is undercut with respect to the second mask layer; and (b) removing a portion of the semiconductor substrate through the open area defined by the second mask layer to form a trench in said semiconductor substrate. An IC device formed using the process is also provided.

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San Jose, CA, United States of America

Duc Q Chau