Cisco Technology, Inc.

Tandem Computers Incorporated

Duc Manh Hoang

Yie-Fong Dan

David Anthony Hughes

Kenneth K Chan

Geoffrey I Iswandhi

Martin W Sanner

Wing M Chan

Sonny N Tran

James E Korpi

Raymond Ng

Jay A Zwagerman

James E Smith

Steven Man Pak Yip

Michael T Chin

Steven G Silverman

Zubair Hussain

David L Bernick

A method to guarantee bandwidth for a terabit multiservice switch including receiving control cells indicating that a destination port of an asynchronous transfer mode (ATM) network is congested, and reducing incoming traffic to the congested port to a guaranteed bandwidth of traffic until the destination port is uncongested, is disclosed.

Guaranteed bandwidth mechanism for a terabit multiservice switch

In a digital computer system which employs a plurality of host processors, at least two system buses and a plurality of peripheral input/output ports, an input/output system is provided whereby ownership of the input/output channels is shared. The device controller employs a first port controller having a first ownership latch, a second port controller having a second ownership latch, a first bus, a dedicated microprocessor having control over the first bus (the MPU bus), a second, higher-speed bus, a multiple-channel direct memory access (DMA) controller which is a state machine which controls the second bus (the data buffer bus), a bus switch for exchanging data between buses, a multiple device peripheral device interface, namely a Small Computer System Interface (SCSI), and at least provision for interface with data communication equipment (DCEs) or data terminal equipment (DTEs). The DMA controller arbitrates data bus usage and can allocate alternate bus clock cycles in response to requests to exchange data and is capable of supporting overlapping transfers. The microprocessor is allowed access to the data buffer bus only if the data buffer bus is not in use for data transfer. The latches associated with each port grant ownership to either port or both ports allowing data exchange between addressed peripheral devices and requesting ports.

Input/output system for multiprocessors

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San Jose, CA, United States of America

Duc Manh Hoang