Sony Corporation

Sony Electronics Inc

Amazon Technologies, Inc.

Duc Hongle Ngo

Mehrdad Nayebi

Chun Yee

Steve Edwards

Gregory Turner Witmer

Patrick Clement Strittmatter

Marcel Colman Eric Stieber

Paul Daniel Everest

Devin Bertrum Pauley

Eric Foxlin

Li Huang

Christopher Wells Fitzhugh

Eric Jeffrey Wei

Allen Weihua Liu

Babak Hashemizadeh

Catherine May Farmer

Merhdad Nayebi

An autonomous mobile device (AMD) builds up electrostatic charges from moving and generates heat from the operation of internal components. In addition to possible user discomfort, electrostatic discharges may damage sensors and electronics. Electrostatic charges are dissipated from the AMD using an electrostatic dissipation structure and conductive wheels. A conductive path between a chassis ground, the electrostatic dissipation structure, and the conductive wheels improves the dissipation of electrostatic charges. Electrostatic charges are also dissipated from components by mounting the components using conductive materials. Sensors may be affixed to a support structure that is affected by thermal expansion. Thermal expansion may distort precise positioning of sensors, reducing accuracy of sensor data. An elastomeric foam may be used to mount sensors to a support structure, allowing for thermal expansion without distorting the positioning of the sensors.

Electrostatic dissipation system for an autonomous mobile device

This disclosure is directed at least partly to reducing an acceleration of a magnet when a magnet is moved toward an attracting object. An apparatus may include a dampening mechanism to dissipate kinetic energy of the magnet as it traverses within a housing from a first position to a second position. The housing may be at least partially coupled to another surface as a result of a magnetic attraction when the magnet is located in the second position. The dampening mechanism may include use of a fluid and/or gas that is displaced by the magnet to slow acceleration of the magnet as the magnet traverses between the first position and the second position. In some embodiments, the dampening mechanism may be implemented using threads that cause rotation of the magnet or by rollers that slow acceleration of the magnet.

Damper for magnetic coupler

A luminance signal generation circuit with single clamp generates a separate luminance signal Y by combining RGB input signals in a weighted manner within a Y-Matrix circuit. During a burst period the single clamping circuit is enabled. When enabled, the single clamping circuit compares the separate luminance signal Y to a constant reference voltage signal. A difference signal, representing the difference between the separate luminance signal Y and the constant reference voltage signal, is used to adjust a blanking level of the RGB input signals until the blanking level of the separate luminance signal Y is equal to the constant reference voltage signal. During the non-burst periods the single clamping circuit is disabled and the Y-Matrix circuit combines the RGB input signals into the separate luminance signal Y. Preferably, the single clamping circuit sets the blank level of the separate luminance signal Y to a level equal to two volts. NPN transistor follower circuits are utilized within the clamping circuit and with input receiving circuits to provide the RGB input signals to the Y-Matrix circuit.

Luminance signal generation circuit with single clamp in closed loop

A driver circuit with pull down npn transistor drives an output voltage signal in response to an input voltage signal, without high-speed pnp transistors. A first npn transistor provides current to the output node when the output node is at a level equal to and less than the level of the input voltage signal less a base-to-emitter junction drop across the first npn transistor. A second npn transistor sinks current from the output node when the output node is at a level greater than the level of the input voltage signal less the base-to-emitter junction drop across the first npn transistor. The second npn transistor is controlled by a level of a control node. When the level of the output node is greater than the level of the input voltage signal less the base-to-emitter junction drop, the first npn transistor is turned off and the level of the control node is charged up by a current source. When the level of the control node reaches a sufficient level, the second npn transistor is turned on and the level of the output voltage signal is decreased.

Driver circuit with pull down npn transistor and gain reduction

A burst gate pulse generator generates a burst gate signal representative of a time period during which a burst signal is present within an input composite video signal. Each period of the input composite video signal includes a horizontal synchronization pulse, a burst signal and a video information signal. The burst gate pulse generator detects the end of the horizontal synchronization signal and begins the burst pulse at the end of the horizontal synchronization signal. A timing circuit including a charge storage device and a charge delivery device controls the duration of the burst pulse. When the burst pulse is activated the charge delivery device begins building a charge across the charge storage device until a threshold value is reached. Once the charge stored across the charge storage device equals the threshold value the burst pulse is deactivated. During the time when the burst pulse is active, the burst signal will be present on the input composite video signal. In order to have a fixed value for a sync tip of the horizontal synchronization pulse and to be able to apply certain thresholds within the burst gate pulse generator, the sync tip of the input composite video signal is clamped to a level equal to 2.5 volts. Preferably, the burst pulse has a duration equal to 3.5 nanoseconds.

Burst gate pulse generator

A burst gate pulse generator circuit generates a burst gate pulse signal representative of a time period during which a burst signal is present within a composite video signal without requiring external components. Each period of the composite video signal includes a horizontal synchronization signal pulse, a burst signal and a video information signal. A pair of integrated capacitors are discharged during the horizontal synchronization pulse. The capacitors are charged at different rates by two current sources after the horizontal synchronization pulse. A first amount of charge across a first capacitor rises above a predetermined threshold level in a first time period. The burst gate pulse signal is activated when the first amount of charge rises above the predetermined threshold level. This occurs before the burst signal is present within the composite video signal. A second amount of charge across a second capacitor rises above the predetermined threshold level in a second time period. The burst gate pulse signal is deactivated when the second amount of charge rises above the predetermined threshold level. This occurs after the burst signal is complete within the composite video signal.

Burst gate pulse generator circuit

A current source and threshold voltage generation circuit generates a current, through a ratio of devices, and a corresponding threshold voltage signal, to be utilized by a timing circuit for generating a timing ramp and determining when the timing ramp crosses the threshold voltage signal. The current is generated through a current generation circuit, using a ratio of matched devices. Preferably, the matched devices are transistors. The current is then utilized by a timing circuit to charge a charge storage device to a level above the level of the threshold voltage signal. The current is also mirrored, appropriately increased and used to generate the threshold voltage signal which is compared to the charge stored on the charge storage device. Accordingly, any errors in the generation of the current are also reflected in the level of the threshold voltage signal, thereby eliminating the potential for errors in the timing ramp signal generated by the timing circuit. Preferably, the charge storage device is a capacitor and the timing circuit is an HHK video circuit. The preferred embodiment of the current source and threshold voltage generation circuit is implemented within an integrated circuit and does not require any external components.

Current source and threshold voltage generation method and apparatus for

A backporch soft-clamp circuit using a servo loop clamps the blank or DC level of a composite video signal to a known value without altering the other components of the signal. The values of the components of the composite video signal are determined by determining their amplitude with respect to the blank level. The backporch soft-clamp circuit sets the blank level to a known value for determining the true value of the components. An output composite video signal is generated which represents the input composite video signal with the blank or pedestal level set to a known DC level. Preferably, the DC level is set to two volts. A burst gate pulse representing the presence of a burst signal within the composite video signal is received by the circuit. During the burst period, the circuit soft clamps the blank level of the output signal to the appropriate level without altering the content of the burst signal. The DC level of the output signal is compared to the appropriate level by a comparator circuit. During the burst period, if the DC level of the output signal is less than the appropriate level, it is raised by a charging circuit. During the burst period, if the DC level of the output signal is greater than the appropriate level, it is lowered by a discharging circuit. During non-burst periods, when the burst signal is not present within the composite video signal, the charging and discharging circuits are disabled and the DC level of the output signal is maintained at a constant level.

Composite video signal backporch soft-clamp system using servo loop

A horizontal synchronization pulse generation circuit generates a horizontal synchronization pulse to be added to an encoded composite video signal. An input receiving circuit receives an encoded input video signal representing video information received from input video signals. An output video signal represents the encoded input video signal in all portions of the signal except the horizontal synchronization period. During the horizontal synchronization period a current is switched through a path resistor and used to generate the voltage level of the horizontal synchronization pulse. The voltage drop across the path resistor during the horizontal synchronization period is applied directly to the output video signal thereby generating a horizontal synchronization pulse. The current switched through the path resistor is generated by a voltage drop across a current resistor. The ratio of the path resistor to the current resistor is matched, allowing the required signal accuracy to be achieved in the voltage drop across the path resistor and generating the appropriate voltage drop across the path resistor according to the current flowing through the current resistor. The horizontal synchronization pulse generation circuit does not clamp the voltage level of the encoded input video signal, but instead generates the horizontal synchronization pulse in reference to the level of the encoded video signal.

Horizontal synchronization pulse generation circuit

A method of and apparatus for selectively engaging an internal trap filter and implementing an external trap filter through a single pin routes a separate luminance signal through the pin or through an internal trap filter based on the logical voltage level at the pin. When implementing an external trap filter the external components comprising the filter are coupled between the pin and ground and a voltage level of the pin is maintained at a logical low voltage level. When the pin is at a logical low voltage level, two path switches are closed and the separate luminance signal is routed through the pin to be filtered by the external trap filter. The internal trap filter is engaged by coupling a precision resistor between the pin and a power supply voltage thereby pulling the voltage level of the pin to a logical high voltage level and opening the two path switches to bypass the pin and route the separate luminance signal through an internal trap filter. When the voltage level of the pin is at a logical high voltage level, a bias switch is closed thereby providing a bias current, created from the voltage drop across the precision resistor, to the internal trap filter. The internal trap filter is activated by the bias current and filters the separate luminance signal according to the value of the bias current, before the separate luminance signal is combined with the separate chrominance signal. The value of the bias current is controlled by the value of the precision resistor.

Method of and apparatus for selectively engaging an internal trap filter

A video/graphics overlay circuit receives an analog input composite video signal and a digital input composite video signal and combines them into a linear combination output composite video signal depending on the state of one or more mixer control signals. The two composite video input signals are each capacitively coupled to buffer and clamp circuits through which the blank or DC level of each signal is clamped to two volts. The outputs of the buffer and clamp circuits are then fed to a mixer circuit and burst separator circuits. The mixer circuit generates the output composite video signal which is a linear combination of the input composite video signals as controlled by the one or more mixer control signals. The burst separator circuits separate the burst signal from the input composite video signals. The extracted burst signals are then provided to a burst signal phase-locked loop for locking the burst signals of the input composite video signals in phase. The feedback loop of the burst signal phase-locked loop is closed through a digital encoder circuit and changes the phase and frequency of the burst signal within the digital input composite video signal until it is locked in phase with the analog input composite video signal. A burst lock signal is generated when the burst signals of the two input signals are locked in phase. A horizontal lock signal is generated when the horizontal sync signals of the two input signals are locked in phase. A black and white detector circuit generates a signal which indicates whether the analog input composite video signal is a black and white signal or a color signal.

Video overlay circuit for synchronizing and combining analog and digital

A luminance signal generation circuit with single clamp and horizontal synchronization pulse generation circuit generates a separate luminance video signal Y, representing RGB input signals, and having a horizontal synchronization pulse. During a burst period, the single clamping circuit compares the separate luminance signal Y to a reference signal. A difference signal, representing the difference between the separate luminance signal Y and the reference signal, is used to adjust a blanking level of the RGB input signals until the blanking level of the separate luminance signal Y is equal to the reference signal. During the non-burst periods, the single clamping circuit is disabled and a Y-matrix circuit combines the RGB input signals into the separate luminance signal Y. A horizontal synchronization pulse generation circuit generates a horizontal synchronization pulse to be added to the clamped separate luminance signal Y. During the horizontal synchronization period, a current is switched through a path resistor and used to generate the voltage level of the horizontal synchronization pulse. The voltage drop across the path resistor during the horizontal synchronization period is applied directly to the output video signal thereby generating a horizontal synchronization pulse. The current switched through the path resistor is generated by a voltage drop across a current resistor. The ratio of the path resistor to the current resistor is matched, allowing the required signal accuracy to be achieved in the voltage drop across the path resistor and generating the appropriate voltage drop across the path resistor according to the current flowing through the current resistor.

An error regulator circuit for use within a charge pump circuit of a phase-locked loop monitors levels of the control signals used to control the charge pump circuit. When one of the control signals remains at a predetermined voltage level for a predetermined period of time, indicating that the charge pump circuit is in a hold mode or an inactive period of time, the current sources within the charge pump used to charge and discharge a charge pump capacitor are temporarily disabled. During a hold or inactive period when one of the control signals used to control the charge pump circuit remains at the predetermined voltage level for more than a predetermined period of time, the current sources of the charge pump circuit are disabled and the charge pump circuit is prevented from charging or discharging the charge pump capacitor until the current sources are re-enabled, thereby allowing the charge pump circuit to maintain an appropriate level of charge across the capacitor during an inactive or hold period. The current sources are re-enabled when the control signal which was at the predetermined voltage level for more than the predetermined period of time is no longer at the predetermined voltage level.

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Hayward, CA, United States of America

Duc Hongle Ngo