Samsung Display Co., Ltd.

Duc-han Cho

Kangnam Kim

Jong-Hyuk Lee

Yong Hee Lee

Beomjun Kim

Jung Hwan Hwang

Bon-Yong Koo

Soo Jin Park

Noboru Takeuchi

Kang Nam Kim

You Mee Hyun

YoonHo Kim

Jong-Moon Park

Beom Jun Kim

Jong Woong Chang

Jeong-Il Kim

Youmee Hyun

A gate driving circuit includes driving stages. Each of the driving stages applies each of gate signals to each of gate lines of a display panel. A k-th (k is a natural number equal to or greater than 2) driving stage includes a first output transistor, a capacitor, and first and second control transistor. The first output transistor includes a control electrode connected to a first node, an input electrode receiving a clock signal, and an output electrode outputting a k-th gate signal. The capacitor is connected between the output electrode of the first output transistor and the control electrode of the first output transistor. The first control transistor applies a first control signal to a second node to control a voltage of the first node before the k-th gate signal is output. The second control transistor is diode-connected between the second node and the first node.

Gate driving circuit and a display device including the gate driving circuit

A display device includes: a plurality of pixels; a plurality of gate lines connected to the plurality of pixels; an output terminal connected to a gate line of the gate lines; a first transistor connected to a first node, a first clock signal input terminal and the output terminal; a second transistor connected to a second clock signal input terminal, a low-level power voltage and the output terminal; a third transistor connected to a second node, the low-level power voltage and the first node; a fourth transistor connected to a first forward input terminal, the low-level power voltage and the second node; and a fifth transistor connected to a first backward input terminal, the low-level power voltage and the second node.

Display device

A thin film transistor array panel includes a gate line elongated in an extension direction and including a gate and dummy gate electrode extended therefrom; and a source electrode, and a single drain member including a drain electrode at a first end thereof and a dummy drain electrode at an opposing second end thereof. The drain electrode faces the source electrode with respect to the gate electrode, and the dummy drain electrode overlaps the dummy gate electrode. The drain and dummy drain electrode respectively include a plurality of first and second regions each having a predetermined width in the extension direction. A second region includes an edge which forms an angle from about 0 degrees to about 90 degrees with the extension direction, and a planar area of at least one of the plurality of second regions is different from that of remaining second regions.

Thin film transistor array panel including angled drain regions

An n-th driving stage of a gate driving circuit includes a first control transistor being configured to increase a voltage of a first node to a first voltage, a control capacitor having one end connected to the first node, a second control transistor being configured to increase the first voltage of the first node to a second voltage that is higher than the first voltage, a third control transistor being configured to increase a voltage of a second node to a third voltage when being turned on according to the voltage applied to the first node, and an output transistor being configured to output a gate signal of the n-th driving stage when being turned on according to the voltage applied to the second node.

Gate driving circuit and display device including the same

A gate driver includes a plurality of stages, wherein an n-th stage includes: a pull-up unit configured to output a high voltage of a clock signal as a high voltage of an n-th gate signal; a pull-down unit configured to decrease the high voltage of the n-th gate signal to a first low voltage; a discharging unit configured to discharge a voltage of the first node to a second low voltage lower than the first low voltage; a carry unit configured to output the high voltage of the clock signal as an n-th carry signal; an inverter unit configured to output a signal in synchronization with the clock signal; a first node storage unit configured to maintain the voltage of the first node at the second low voltage; and a second node storage unit configured to maintain the voltage of the second node at the first or second low voltage.

Gate driver and a display device including the same

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Seoul, South Korea

Duc-han Cho