American Telephone & Telegraph Co., At&t Bell Laboratories

Duane R Aadsen

Charles E Stroud

Sunil K Jain

A memory array included with logic circuitry on an integrated circuit is tested by a technique that reads and writes a specified sequence of test bits into a given memory word before progressing to the next word. A checkerboard pattern of 1's and 0's is written into the physical memory locations. This provides for an improved worst-case test while allowing case of implementation for the test circuitry. The test results from a comparator circuit may be compressed to provide one (or a few) test flags indicating whether the memory passed the test, requiring a minimal number of test pads or terminals for the chip.

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Moores Township, Northampton County, PA, United States of America

Duane R Aadsen