Agere Systems Inc.

Lucent Technologies Inc.

Duane J Loeper

Dipankar Bhattacharya

John Christopher Kriz

Yehuda Smooha

Bernard Lee Morris

Richard Joseph McPartland

Makeshwar Kothandaraman

Antonio M Marques

Amit Kumar Banerjee

Che Coi Leung

An ESD clamp circuit for use between separate power rails. An ESD clamp is based on a wide nMOSFET. A symmetrical circuit is designed vis-&#xe0;-vis the two power rails, with respect to ground, allowing discharge of an ESD surge in both polarities of stress. An nMOSFET device drives the gate of a large nMOSFET (e.g., having a device width between 1000 and 10,000 microns). The large power rail-to-power rail nMOSFET has its gate controlled by the output inverter stage of either ESD detection circuit connected to a respective power supply rail. The gate is switched to a common ground during normal operation of the integrated circuit.

Power pin to power pin electro-static discharge (ESD) clamp

A circuit for defining a voltage potential of a floating well in which is formed at least one metal-oxide-semiconductor device includes a sense circuit operative to detect a voltage at a node to which the floating well is connected and to generate a control signal indicative of whether the voltage at the node is substantially within a voltage range. A lower value of the voltage range is substantially equal to a threshold voltage below a first supply voltage of the circuit. An upper value of the voltage range is substantially equal to a threshold voltage above the first supply voltage. The circuit for defining the voltage potential of the floating well further includes a voltage generator circuit operative to receive the control signal and to generate a bias signal for setting a voltage potential of the well in response to the control signal, the bias signal being controlled throughout the voltage range.

Floating well circuit having enhanced latch-up performance

A PUR circuit for generating a reset signal includes a first node for receiving a reference voltage and a second node for receiving a supply voltage that is referenced with respect to the reference voltage. The circuit further includes a voltage level detector coupled between the first node and a third node, the voltage level detector being configured to generate a first control signal at the third node. The voltage level detector includes a first transistor having a first threshold voltage associated therewith. A resistance element is coupled between the second node and the third node, the resistance element having a first resistance value associated therewith. The circuit also includes an inverter having an input coupled to the third node and having an output for generating a second control signal in response to the first control signal. The inverter includes a second transistor having a second threshold voltage associated therewith which is lower than the first threshold voltage. The voltage level detector is configured such that the first control signal is substantially equal to the supply voltage when the supply voltage is less than a first voltage, and the first control signal is equal to a second voltage when the supply voltage is substantially equal to or greater than the first voltage. The second voltage is less than a lower switching point of the inverter, the first voltage being based at least in part on the first threshold voltage, the reset signal being a function of the second control signal.

Programmable reset signal that is independent of supply voltage ramp rate

An integrated circuit-based charge pump generates an output voltage having a greater magnitude than a power supply voltage. The charge pump has a charge pump section having a plurality of alternating stages driven by first and second alternating, non-overlapping clock signals, said plurality of alternating stages including an input stage for receiving the power supply voltage and an output stage for generating at a last stage node a last stage voltage having a greater magnitude than the power supply voltage. A gating transistor is coupled at a drain terminal to the last stage node, wherein the gating transistor is clocked by one of said clock signals and is biased so that the gating transistor, during a boost phase, gates the last stage voltage to a load coupled to the source terminal of the gating transistor without a voltage drop and, at other times, turns off to prevent charge from flowing from the load into the last stage node of the charge pump section.

Charge pump with no diode drop at output stage

An integrated circuit memory array has a plurality of rows of memory cells. The rows of the memory array are divided into a plurality of words. Each memory cell is in a column of the memory array, and is coupled at an output terminal to a prechargeable column output line for the column. Each memory cell of a given word is coupled at a source terminal to a local source line for the word. The local source line for each word of the memory array is selectively coupleable to ground.

Growing community of inventors

Spring City, PA, United States of America

Duane J Loeper