Intel Corporation

Duane G Quiet

Huimin Chen

Amit Kumar Srivastava

Kenneth Foust

Robert A Dunstan

Harry G Skinner

Ajay V Bhatt

David J Harriman

Hormuzd M Khosravi

David I Poisner

Aleksander Magi

Andrew M Volk

Richmond Hicks

Peter D MacWilliams

Wah Yiu Kwong

Gary A Solomon

Ken Drottar

James E Akiyama

Willem M Beltman

Vivek Paranjape

Liang Cheng

Christopher J Lord

Dennis Bell

Terry L Baucom

Lili Ma

Venkataramani Gopalakrishnan

Hemin Han

Amir Bashir

Satish Ramanathan

Naveed Khan

Vishnu Balraj

Garrett Hall

Shrestha Sinha

Ravishankar Subramanian

Terry Lauer

Arunima Kashyap

Embodiments are directed toward apparatuses, systems, and methods to implement policies for dynamically switching between an integrated graphics mode and a discrete graphics mode for providing a display signal to an external USB Type-C port. Some embodiments include a controller configured to provide signals to a first multiplexer and to a second multiplexer, and based on a platform policy, control the at least first or the second multiplexer to dynamically switch to the first graphics mode to output signals received from an integrated graphics controller to the external USB Type-C port or to switch to the second graphics mode to output signals received from a discrete graphics controller to the external USB Type-C port. Other embodiments may be described and/or claimed.

Apparatuses, systems, and methods for dynamically switching graphics modes for providing a display signal

In an embodiment, a host device includes: a transceiver to communicate information on an interconnect; a controller to control operation of the transceiver and to be a master for the interconnect; and a role transfer logic to cause a secondary device to be the master for the interconnect when at least a portion of the host device is to enter into a low power. Other embodiments are described and claimed.

Method, apparatus and system for role transfer functionality for a bus master

Embodiments of the present disclosure may relate to a host controller that includes processing circuitry to identify an inter-integrated circuit (IC) out-of-band interrupt (OBI) received on a general purpose input-output (GPIO) pin from an IC device that is unable to generate an improved inter-integrated circuit (I3C) bus an I3C in-band interrupt (IBI). The processing circuitry may further generate, based on the IC OBI, an I3C IBI that includes information related to the IC OBI. The host controller may further include transmission circuitry to transmit the I3C IBI on an I3C bus. Other embodiments may be described and/or claimed.

Out-of-band interrupt mapping in MIPI improved inter-integrated circuit communication

Out-of band interrupt mapping in MIPI improved inter-integrated circuit communication

In one embodiment, a host controller is to couple to an interconnect to which a plurality of devices may be coupled. The host controller may include: a first driver to drive first information onto the interconnect; and a first receiver to receive second information comprising parameter information of at least one of the plurality of devices from the interconnect. The host controller may further include an integrity control circuit to receive the parameter information of the at least one of the plurality of devices and dynamically update at least one capability of the host controller based at least in part on the parameter information. Other embodiments are described and claimed.

Method, apparatus and system for dynamic optimization of signal integrity on a bus

In one embodiment, an apparatus includes a clock control circuit to generate a clock signal for communication on an interconnect. The clock control circuit may be configured to receive an indication of a next device of a plurality of devices to be accessed and to dynamically update a control signal to cause the communication of the clock signal to be dynamically switched between a fixed clock frequency and a spread spectrum clock frequency based at least in part on the indication of communication to the next device. Other embodiments are described and claimed.

Method, apparatus and system for dynamic clock frequency control on a bus

A system and method is described for simplifying implementation of repeater (e.g., re-driver/re-timer) module implementation in high-data-rate interconnects that carry a relatively low-data-rate clock signal as well as the data stream (e.g., PCIe). At the endpoint, any information critical to the function of the repeater (e.g., the most recent data rate negotiated by a pair of endpoints communicating through the repeater) is embedded in the clock signal by pulse-width modulation as ordered sets. The repeater only needs to read the clock-embedded information rather than decoding the data stream. Thus repeaters for such applications reconstruct the high-rate data-stream while actually decoding only the low-rate clock signal. Because the clock-signal protocol is independent of the data-stream protocol, the repeater's operation is protocol-agnostic with respect to the data-stream.

Digital interconnects with protocol-agnostic repeaters

The subject innovation relates to an apparatus that includes an integrated case with all parts disposed within. The apparatus includes a processor, at least two displays, at least two cameras, and a storage system. The storage system comprises code to direct the processor to obtain input from the at least two cameras, and provide display information to the at least two displays.

Dual display system

A system can include a host device and a remote terminal. The host device can include a host terminal, the host terminal including a host configuration manager to allocate a data lane to an I/O protocol and a protocol multiplexer to carry out allocation of the data lane based on the allocation of the configuration manager. The remote terminal can include a remote configuration manager. The remote configuration manager is to communicate with the remote configuration manager via a control bus to detect connection of an I/O device to an I/O port and to allocate the data lane to the I/O protocol.

Lane division multiplexing of an I/O link

Systems and methods may provide for implementing dynamically adaptive frequency adjustment. In one example, the method may include analyzing a first set of transmission information and a second set of transmission information based on a likelihood of transmission interference, and determining a dynamically adapted camera frequency, wherein the dynamically adapted camera frequency is to minimize the transmission interference.

Dynamically adaptive frequency adjustments

An example of an electronic device with a first camera and a second camera is described. The first camera receives a first image stream, and the second camera receives a second image stream that includes a face of a user of the electronic device. The electronic device also includes a camera control module that identifies gesture based on a change in the second image stream, identifies a camera control feature of the first camera based on the gesture, and activates the camera control feature for the first camera.

Controlling a camera with face detection

A system and method for implementing integrated and adjustable image projection with auto-image correction in electronic devices using an in-facing or world-facing image projector are disclosed. A particular embodiment includes an electronic device including: a lid; a base including a hinge coupling the lid with the base; and an image projection subsystem including an image projector installed in the lid, the image projector being configured to produce a projected image that is projected onto a projection surface, the angle of the projection being adjustable by adjusting the angle of the lid relative to the base.

Integrated and adjustable image projection with auto-image correction in electronic devices using an in-facing or world-facing image projector

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Hillsboro, OR, United States of America

Duane G Quiet