Unisys Corporation

Duane A Schroeder

Douglas A Fuller

Kenichi Tsuchiya

David M Hime

A self-timing clock generator for use with a precharged Static Random Access Memory (SRAM). The invention asynchronously switches the memory clock pulse to a precharge signal upon recognition of completion of a memory access cycle. Recognition of completion of the memory access cycle is performed in one of two ways. The first method monitors for the existence of a preprogrammed memory-completion bit which becomes active at the same time that read or write data becomes valid at the data outputs. The second method monitors for the existence of a memory-completion bit generated through the use of an odd parity generator. An alternate clocking method is provided to bypass the asynchronous self-timing clock generator, and to allow for synchronous clocking of the precharged SRAM. An external clocking method is also provided to directly clock the precharged SRAM. Finally, the self-timing clock generator and the precharged SRAM may be tested through the use of a test enable circuit, which intercepts the generated precharge and clock signals, and provides in place thereof a test precharge and clock signal.

Self-timing clock generator for precharged synchronous SRAM

A test circuit for two level latches on an integrated circuit to be tested includes a test enable driver circuit coupled to a third level switch which is connected in series between the latches to be tested and a low voltage source. The third level switch converts the two level latches to be tested into a buffer such that data applied as an input to the two level latches appears in identical form as data at the output pin of the integrated circuit chip.

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White Bear Lake, MN, United States of America

Duane A Schroeder