Intel Corporation

Dror Markovich

Ilan Pardo

Oren Ben-Kiki

Yuval Yosef

Robert Valentine

Eliezer Weissmann

Oren Kedem

Ran Mor

Nir Paz

Igor Brainman

Alon Pais

Jesus Corbal

Amit Gradstein

Thomas D Fletcher

Dennis Ryan Bradford

Jonathan Cannon Hall

Brian J Hickmann

Michael Behar

Gregory W Chance

Nebil Tanzi

Wayne Ballantyne

Bruce Geren

Peter Pawliuk

For example, a first STA may be configured to transmit to a second STA a message including a first value to indicate an available memory size at the first STA at a beginning of a TXOP, and a second value to indicate a maximal length of an A-MPDU transmission during the TXOP; to receive an initial A-MPDU from the second STA during the TXOP, a length of the initial A-MPDU is not longer than the first value; to determine a capacity value based on a current available memory size at the first STA, the capacity value to indicate whether the second STA is to be allowed to send to the first STA a subsequent A-MPDU having a length which is not longer than the second value; and to transmit to the second. STA an Ack including a buffer capacity field including the capacity value.

Apparatus, system and method of communication during a transmit opportunity (TXOP)

In a communication device and corresponding methods, a hierarchical, reduced power, beam search process includes a hierarchical activation of the radio frequency frontend (RFFE), transceiver, and baseband integrated circuit (BBIC) for a beam searching operations. For example, a first signal metric measurements can be performed to determine signal information. An operating mode can be determined based on the signal information. In a first operating mode, one or more second signal metric measurements can be performed for a subset of beamforming configurations of the wireless communication device to determine beamforming information. In a second operating mode, one or more third signal metric measurements can be performed on the beamforming configurations to determine the beamforming information.

Communication scanning method and system

For example, a first STA may be configured to transmit to a second STA a message including a first value to indicate an available memory size at the first STA at a beginning of a TXOP, and a second value to indicate a maximal length of an A-MPDU transmission during the TXOP; to receive an initial A-MPDU from the second STA during the TXOP, a length of the initial A-MPDU is not longer than the first value; to determine a capacity value based on a current available memory size at the first STA, the capacity value to indicate whether the second STA is to be allowed to send to the first STA a subsequent A-MPDU having a length which is not longer than the second value; and to transmit to the second STA an Ack including a buffer capacity field including the capacity value.

An apparatus and method are described for executing both latency-optimized execution logic and throughput-optimized execution logic on a processing device. For example, a processor according to one embodiment comprises: latency-optimized execution logic to execute a first type of program code; throughput-optimized execution logic to execute a second type of program code, wherein the first type of program code and the second type of program code are designed for the same instruction set architecture; logic to identify the first type of program code and the second type of program code within a process and to distribute the first type of program code for execution on the latency-optimized execution logic and the second type of program code for execution on the throughput-optimized execution logic.

Apparatus and method for a hybrid latency-throughput processor

A processor having one or more processing cores is described. Each of the one or more processing cores has front end logic circuitry and a plurality of processing units. The front end logic circuitry is to fetch respective instructions of threads and decode the instructions into respective micro-code and input operand and resultant addresses of the instructions. Each of the plurality of processing units is to be assigned at least one of the threads, is coupled to said front end unit, and has a respective buffer to receive and store microcode of its assigned at least one of the threads. Each of the plurality of processing units also comprises: i) at least one set of functional units corresponding to a complete instruction set offered by the processor, the at least one set of functional units to execute its respective processing unit's received microcode; ii) registers coupled to the at least one set of functional units to store operands and resultants of the received microcode; iii) data fetch circuitry to fetch input operands for the at least one functional units' execution of the received microcode.

Processing core having shared front end unit

A processor includes an instruction schedule and dispatch (schedule/dispatch) unit to receive a single instruction multiple data (SIMD) instruction to perform an operation on multiple data elements stored in a storage location indicated by a first source operand. The instruction schedule/dispatch unit is to determine a first of the data elements that will not be operated to generate a result written to a destination operand based on a second source operand. The processor further includes multiple processing elements coupled to the instruction schedule/dispatch unit to process the data elements of the SIMD instruction in a vector manner, and a power management unit coupled to the instruction schedule/dispatch unit to reduce power consumption of a first of the processing elements configured to process the first data element.

Vector mask driven clock gating for power efficiency of a processor

An apparatus and method are described for providing low-latency invocation of accelerators. For example, a processor according to one embodiment comprises execution logic to execute a plurality of instructions including an accelerator invocation instruction to invoke one or more accelerator commands. The accelerator invocation instruction stores command data specifying the command within a command register. One or more accelerators read the command data from the command register and responsively attempt to execute the command identified by the command data. Upon a switch from a first context to a second context, an accelerator context save/restore pointer identifies a region within system memory where the accelerator is to save its state and later the accelerator context save/restore pointer aids in restoring its state upon returning to the first context.

Apparatus and method for low-latency invocation of accelerators

An apparatus and method are described for providing low-latency invocation of accelerators. For example, a system according to one embodiment comprises: a processor includes a plurality of simultaneous multithreading (SMT) cores, at least one shared cache circuit to be shared among two or more of the SMT cores; and at least one of the SMT cores including at least one level 2 (L2) cache circuit to store both instructions and data and communicatively coupled to the instruction cache circuit and the data cache circuit, a communication interconnect circuit including a peripheral component interconnect express (PCIe) circuit to communicatively couple one or more of the SMT cores to an accelerator device and a memory access circuit to identify an accelerator context save/restore region in a memory responsive to a context save/restore value, the accelerator context save/restore region to share an accelerator context state.

An apparatus and method are described for providing low-latency invocation of accelerators. For example, a processor according to one embodiment comprises: a plurality of simultaneous multithreading (SMT) cores, at least one shared cache circuit to be shared among the SMT cores, and at least one L2 cache circuit to store both instructions and data. The processor further comprises a communication interconnect circuit including a PCIe circuit to communicatively couple one or more of the SMT cores to an accelerator device, the PCIe circuit to provide the accelerator device access to resources of the processor including the at least one shared cache circuit. The processor further comprises a memory access circuit to identify an accelerator context save/restore region in a memory determined by an accelerator context save/restore value, the accelerator context save/restore region to store an accelerator context state.

An apparatus and method are described for providing low-latency invocation of accelerators. For example, a processor according to one embodiment comprises: a command register for storing command data identifying a command to be executed; a result register to store a result of the command or data indicating a reason why the command could not be executed; execution logic to execute a plurality of instructions including an accelerator invocation instruction to invoke one or more accelerator commands; and one or more accelerators to read the command data from the command register and responsively attempt to execute the command identified by the command data.

A processor is described comprising: an architectural register file implemented as a combination of a register file cache and an architectural register region within a level 1 (L1) data cache, and a data location table (DLT) to store data indicating a location of each architectural register within the register file cache and/or the architectural register region within the L1 data cache.

Growing community of inventors

Tel Aviv, Israel

Dror Markovich