Tensilica, Inc.

Cadence Design Systems, Inc.

Babblelabs LLC

Silicon Graphics, Incorporated

Dror E Maydan

Christopher Rowen

Walter David Lichtenstein

Albert Ren-Rui Wang

Earl A Killian

David W Goodwin

Ricardo E Gonzalez

Robert P Wilson

John C Ruttenberg

Ashish B Dixit

Monica Lam

Samer Lutfi Hijazi

Pavlos Konas

Christopher Mark Songer

Darin Stamenov Petkov

Rangarajan Srinivasan

Akilesh Parameswar

Richard Ruddell

Marines Puig Medina

Nupur Bhattacharyya

Kamil Krzysztof Wojcicki

Raul Alejandro Casas

Sachin P Ghanekar

Peng Tu

Ding-Kai Chen

Steven Weng-Kiang Tjiang

Fei Sun

William A Huffman

James C Dehnert

Sun C Chan

Xuehong Mao

Hua Mu

Darin S Petkov

Marcin Ciolek

Erik S Panu

Pushkar G Patwardhan

Weng Kiang Tjiang

Darin Stemenov Petkov

Michael Wolf

Jack C Carter

Samir S Pathak

Systems and methods are disclosed for data driven radio enhancement. For example, methods may include demodulating a radio signal to obtain a demodulated audio signal; determining a window of audio samples based on the demodulated audio signal; applying an audio enhancement network to the window of audio samples to obtain an enhanced audio segment, in which the audio enhancement network includes a machine learning network that has been trained using demodulated audio signals derived from radio signals; and storing, playing, or transmitting an enhanced audio signal based on the enhanced audio segment.

Data driven radio enhancement

Systems and methods are disclosed for audio group identification for conferencing. For example, methods may include joining a conference call using a network interface; accessing an audio signal that has been captured using a microphone; detecting a control signal in the audio signal; and, responsive to detection of the control signal, invoking modification of an audio path of the conference call.

Audio group identification for conferencing

Systems and methods are disclosed for audio enhancement. For example, methods may include accessing audio data; determining a window of audio samples based on the audio data; inputting the window of audio samples to a classifier to obtain a classification, in which the classifier includes a neural network and the classification takes a value from a set of multiple classes of audio; selecting, based on the classification, an audio enhancement network from a set of multiple audio enhancement networks; applying the selected audio enhancement network to the window of audio samples to obtain an enhanced audio segment, in which the selected audio enhancement network includes a neural network that has been trained using audio signals of a type associated with the classification; and storing, playing, or transmitting an enhanced audio signal based on the enhanced audio segment.

Data driven audio enhancement

A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

Automated processor generation system and method for designing a configurable processor

A system and method for preventing an application program, which is licensed to a customer to be exclusively executed in a processor based on a certain processor design, from being executed properly in unauthorized processors is provided. The system includes a scrambling module and a recovery module. The scrambling module scrambles a selected portion of the application program using an identifier which identifies the authorized processor design. The recovery module adds an unscrambling program to the application program such that when the program is running in a processor, it retrieves a second identifier from the processor and unscrambles the scrambled portion of the application program using the retrieved second identifier. If the second identifier does not correspond to an authorized processor design, the unscrambling operation will incorrectly unscramble the scrambled portion and the application program will not run properly.

System and method for preventing proper execution of an application program in an unauthorized processor

Systems and method for automatically generating a set of shared processor datapaths from the description of the behavior of one or more ISA operations is presented. The operations may include, for example, the standard operations of a processor necessary to support an application language such as C or C++ on the ISA. Such operations, for example, may represent a configurable processor ISA. The operations may also include one or more extension operations defined by one or more designers. Thus, a description of the behaviors of the various standard and/or extension operations that compose the ISA of an instance of a standard or configurable processor is used to automatically generate a set of shared processor datapaths that implement the behavior of those operations.

Method and system for automatic generation of processor datapaths

A microprocessor includes a memory interface to obtain data envelopes of a first length, and control logic to implement an instruction to load an initial data envelope of a stream of data values into a buffer, each data value having a second length shorter than the first length, the stream of data values being disposed across successive data envelopes at the memory interface. Another instruction merges current contents of the buffer and the memory interface such that each invocation loads one of the data values into a first register, and moves at least a remainder of the current contents of the memory interface into the buffer for use in a successive invocation. Another instruction loads a reversed representation of a set of data values obtained via the memory interface into a second register. Another instruction implements an FIR computation including a SIMD operation involving multiple data values of the stream and the reversed representation.

Audio digital signal processor

An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.

System and method of designing instruction extensions to supplement an existing processor instruction set architecture

System and method of customizing an existing processor design having an existing processor instruction set architecture with instruction extensions

Systems and method for automatically generating a set of shared processor datapaths from the description of the behavior of one or more ISA operations is presented. The operations may include, for example, the standard operations of a processor necessary to support an application language such as C or C++ on the ISA. Such operations, for example, may represent a configurable processor ISA. The operations may also include one or more extension operations defined by one or more designers. Thus, a description of the behaviors of the various standard and/or extension operations that compose the ISA of an instance of a standard or configurable processor is used to automatically generate a set of shared processor datapaths that implement the behavior of those operations. In addition, certain aspects may take one or more operations as well as one or more input semantics and either re-implement the input semantics automatically, or combine the input semantics with each other or with one or more other operations to automatically generate a new set of shared processor datapaths.

Automated processor generation system for designing a configurable processor and method for the same

A digital computer system automatically creates an Instruction Set Architecture (ISA) that potentially exploits VLIW instructions, vector operations, fused operations, and specialized operations with the goal of increasing the performance of a set of applications while keeping hardware cost below a designer specified limit, or with the goal of minimizing hardware cost given a required level of performance.

Automatic instruction set architecture generation

Method and system for automatic generation of processor datapaths using instruction set architecture implementing means

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Palo Alto, AZ, United States of America

Dror E Maydan