Saifun Semiconductors Ltd.

Intel Corporation

Dror Avni

Boaz Eitan

Assaf Shappir

Philip L Cloud

Peter D MacWilliams

Robert L Farrell

Anan Baransy

Avi Liebermensch

Avi Avraham

Daniel G Genossar

A method and a system for operating bits of memory cells in a memory array, the method including applying a first operating pulse to a terminal of a first cell, the first operating pulse is intended to place the first cell into a predefined state; and applying a second operating pulse to a terminal of a second cell in the set, the second operating pulse is intended to place the second cell to the predefined state, and the pulse characteristics of the second operating pulse are a function of the response of the first cell to the first operating pulse.

Method, system, and circuit for operating a non-volatile memory array

Method for operating a memory device

A method for programming and erasing a memory array includes the step of adapting programming or erase pulses to the current state of the memory array. In one embodiment, the step of adapting includes the steps of determining the voltage level of the programming pulse used to program a fast bit of the memory array and setting an initial programming level of the memory array to a level in the general vicinity of the programming level of the fast bit. For erasure, the method includes the steps of determining erase conditions of the erase pulse used to erase a slowly erasing bit of said memory array and setting initial erase conditions of said memory array to the general vicinity of said erase conditions of said slowly erasing bit. In another embodiment of the array, the step of adapting includes the steps of measuring the current threshold level of a bit to within a given range and selecting an incremental voltage level of a next programming or erase pulse for the bit in accordance with the measured current threshold level.

Programming and erasing methods for a non-volatile memory cell

A method for operating bits of memory cells in a memory array, the method including applying operating pulses to bits of a sample of memory cells, determining a response of at least one of an electrical, physical and mechanical property (e.g., threshold voltage) of the bits to the operating pulses, and applying at least one further operating pulse to the rest of the array, the at least one further operating pulse being a function of the response.

A power conservation apparatus in a computer system. This apparatus includes an identification register in a processor comprising a contents including a plurality of flags for identifying the characteristics of the processor. One of these characteristics may be whether the processor includes static logic devices. In such systems, the clock connected to the processor may be halted, without the corruption of data in the processor. Other characteristics may include whether the processor is clocked at the same rate as the system, or whether the processor may operate on a lower voltage power source. The apparatus further comprises a transmission circuit for transferring the contents of the identification register from the processor to a system coupled to the processor upon the receipt of a first code. The apparatus also comprises a reception circuit in the system for receiving the contents of the identification register, a storage circuit for storing the contents of the identification register, a determination circuit in the system for determining the contents of the storage circuit, such as a logic unit, and a clock halt circuit for stopping the clock. In this manner, various characteristics of the processor may be determined allowing the system to be reconfigured and power conserved appropriately.

Register for identifying processor characteristics

A power conversation apparatus in a computer system. This apparatus includes an identification register in a processor comprising a contents including a plurality of flags for identifying the characteristics of the processor. One of these characteristics may be whether the processor includes static logic devices. In such systems, the clock connected to the processor may be halted, without the corruption of data in the processor. Other characteristics may include whether the processor is clocked at the same rate as the system, or whether the processor may operate on a lower voltage power source. The apparatus further comprises a transmission circuit for transferring the contents of the identification register from the processor to a system coupled to the processor upon the receipt of a first code. The apparatus also comprises a reception circuit in the system for receiving the contents of the identification register, a storage circuit for storing the contents of the identification register, a determination circuit in the system for determining the contents of the storage circuit, such a logic unit, and a clock halt circuit for stopping the clock. In this manner, various characteristics of the processor may be determined allowing the system to be reconfigured and power conserved appropriately.

A method and apparatus for synchronizing an asynchronous signal to a clock signal. The apparatus includes an enable generator, first, second and third sampling circuits, a selecting circuit, and can include a latching circuit. The enable generator is coupled to the first sampling circuit by a first enable line, to the second sampling circuit by a second enable line, and to the third sampling circuit by a third enable line. The first, second, and third sampling circuits are coupled to receive the asynchronous signal. The selecting circuit is coupled to receive the output signals of the first, second and third sampling circuits. For the first sampling circuit, the following steps are performed: sampling the asynchronous signal, generating an output signal for the sampling circuit, waiting a period of time, and selecting the sampling circuit's output signal. These steps are also performed for the second sampling circuit and the third sampling circuit.

Parallel multistage synchronization method and apparatus

A dual mode input buffer having two modes of operation, a first mode of operation which provides a first CMOS level output from a TTL level input while operating at a first voltage level, and a second mode of operation which provides a second CMOS level output from a TTL level input while operating at a second voltage level. A first input provides TTl level inputs. An output provides a first CMOS level output and a second CMOS level output, one at at a time, depending on the mode of operation. A second input selects one of the two operation modes. Buffer means provides buffering of the signals provided on the first input. The buffer means has a level shifting transistor. Trip point level shifting means is provided for maintaining the trip point of the dual mode input buffer at approximately the same voltage level when the dual mode input buffer is operated at the second voltage level as when it operates at the first voltage level. A second input activates said trip point level shifting means.

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Haifa, Israel

Dror Avni