Cypress Semiconductor Corporation

Drew Marshall Harrington

Paul F Beard

Warren S Snyder

Scott Allen Swindle

Mark D Moore

A Programmable System on a Chip Hub (PHUB) is configured to enable master processing elements within the PHUB to simultaneously access peripherals on different busses. The master processing elements include a Central Processing Unit (CPU) interface configured to decode addresses received from a CPU and configure the PHUB to connect signaling from the CPU to one of the multiple busses associated with the address. A second one of the master processing elements is a Direct Memory Access Controller (DMAC) source engine configured to conduct Direct Memory Access (DMA) reads. A third one of the master processing elements is a DMAC destination engine configured to conduct DMA writes independently of the CPU interface.

Programmable system-on-chip hub

A plurality of arbitration devices is hierarchically coupled and has a plurality of child devices and at least one parent device. Each of the plurality of arbitration devices is operable to store a previous arbitration winner. In addition, the plurality of arbitration devices is operable to generate a request-out signal based on a plurality of request-in signals, and is operable to generate a select-out signal from a select-in signal, a plurality of request-in signals and from the previous arbitration winner. The request-out signals of the plurality of child devices are coupled to request-in signals of their respective parent devices and select-in signals of the child devices are received from select-out signals of the respective parent devices. Access is granted by a select-out signal from a device of the plurality of arbitration devices that resides at the lowest level of the system.

Hierarchically expandable fair arbiter

A method for radiofrequency (RF) transmission of digital information includes generating an RF signal using a voltage-controlled oscillator (VCO), stabilizing the RF signal from the VCO by providing an error signal from a phase-locked loop (PLL) to an input of the VCO, and combining the digital information with the error signal of the PLL input to the VCO, thereby causing variations in frequency of the RF signal from the VCO that represent the digital information. Apparatus for RF transmission of digital information includes a VCO, the VCO arranged to generate an RF signal, a PLL, the frequency input of the PLL coupled to the RF signal output of the VCO, an encoder, the encoder arranged to convert the digital information into a form where it has a data rate faster than a response time of the PLL, and a coupler, the coupler coupling both the error signal output of the PLL and the encoded digital information to an input of the VCO.

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Oakland, CA, United States of America

Drew Marshall Harrington