Advanced Micro Devices Corporation

Standard Microsystems Corporation

Other

Siemens Industry, Inc.

Drew Jon Dutton

Douglas D Gephardt

Steven L Belt

Brett B Stewart

Rita M Wisor

David S Christie

James R MacDonald

Sherman E Lee

William M Johnson

Scott E Swanstrom

Andy Lambrecht

David W Stoenner

Timothy A Olson

Stephen Cox

Alan David Berenbaum

J Andrew Lambrecht

Raphael Weiss

Ian F Harris

Scott A White

Dale E Gulick

Brian C Barnes

Michael T Wisor

Henry Wurzburg

Dan S Mudgett

Richard Wahler

Steve L Belt

Kenneth W Gay

Robert C Bartmess

Suman Olney

Simeon K Iliev

Steve Cox

Douglas A Hooks

Systems, methods, and mediums use temperature weighting in energy-usage measurements. A method includes identifying a number of days that each of a plurality of different temperatures occurred at a location during a period of time. The method includes identifying a baseline for initial energy usage at a building located in the location. The method includes receiving measurements for energy usage at the building. The method includes generating an expression for measured energy usage as a function of temperature by performing a regression analysis on the measurements for energy usage. The method includes identifying a difference between the baseline for initial energy usage and the expression for measured energy usage. The method includes generating a weighting for the difference between baseline energy usage and the measured energy usage at one or more temperatures based on the number of days the one or more temperatures occurred during the period of time.

Methods and systems for measurement and verification weighting with temperature distribution

An interlocking, compressible spoke wheel system having a ring of paired spokes. The locking of left and right spokes into pairs provides improved tire displacement under loads. The left and right half wheels formed by sets of left spokes and right spokes. enable a novel mounting system for the wheel rim or tire to attach to the spoke system.

Interlocking compressible, paired spoke wheel system

In various embodiments, a computer system may include a computer controller to send and/or receive sideband signals to/from a USB device. In some embodiments, the USB device may include a USB controller to send/receive sideband signals to/from the computer controller. The computer controller and USB controller may allow communications between the computer system and the USB device when either of the computer system or USB device is in a low power state. The sideband signal sent between the computer system and the USB device may trigger the other of the computer system or USB device to enter a normal power state. In some embodiments, the computer controller and/or USB controller may be further coupled to a memory to buffer data to be sent to the computer system or USB device after the computer system or USB device returns to a normal power state.

Power managed USB for computing applications using a controller

A system including a serialized secondary bus architecture. The system may include an LPC bus, an I/O controller, a serialized secondary bus, and at least one slave device. The LPC bus may be connected to the I/O controller, and the at least one slave device may be connected to the I/O controller via the serialized secondary bus. The serialized secondary bus has a reduced pin count relative to the LPC bus. The I/O controller may receive bus transactions from the LPC bus. The I/O controller may translate and forward LPC bus transactions to the at least one device over the secondary bus. The I/O controller may include a processing unit. The processing unit may initiate bus transactions intended for the at least one slave device. The I/O controller may also include a bus arbitration unit. The bus arbitration unit may arbitrate ownership of the secondary bus between the processing unit and the LPC bus.

Serialized secondary bus architecture

System and method for determining closure of an electronic device. The electronic device may include a top portion and a bottom portion, and may be connecting via a hinge or other closing mechanism. The top portion and/or the bottom portion may include one or more capacitive sensors which provide signals corresponding to physical contact and a controller coupled to the one or more capacitive sensors. The controller may operate to receive the signals from the one or more capacitive sensors, determine if the electronic device has been closed based on the received signals, and initiate a sequence of events corresponding to the closure of the electronic device. The sequence of events may result in the device entering a low power state.

Detecting closure of an electronic device using capacitive sensors

Low cost fingerprint system having a single chip solution includes a circuit board, a fingerprint sensor array fabricated onto a first surface of the circuit board, and an integrated circuit die for processing information received from the fingerprint sensor array is mounted directly to a second surface of the circuit board. The integrated circuit die may be electrically connected to the sensor by, for example, vias in the circuit board.

Low cost fingerprint sensor system

System and method for sharing a device, e.g., non-volatile memory, between a host processor and a microcontroller. In response to system state change to a first state wherein the microcontroller is assured safe access to the non-volatile memory (e.g., in response to power-on reset, system reset, sleep state, etc.), the microcontroller holds the system in the first state (e.g., system reset), and switches access to the non-volatile memory from the processor to the microcontroller. While the system is held in the first state, the microcontroller accesses the device (e.g., non-volatile memory), e.g., fetches program instructions/data from the non-volatile memory and loads the program instructions/data into a memory of the microcontroller. After the access, the microcontroller changes or allows change of the system state, e.g., switches access to the device, e.g., the non-volatile memory, from the microcontroller to the processor, and releases the system from the first state.

Sharing non-sharable devices between an embedded controller and a processor in a computer system

System and method for performing pre-boot security verification in a system that includes a host processor and memory, an embedded microcontroller with an auxiliary memory, e.g., an on-chip ROM, or memory controlled to prohibit user-tampering with the contents of the memory, and one or more pre-boot security components coupled to the embedded microcontroller. Upon power-up, but before host processor boot-up, the embedded microcontroller accesses the auxiliary memory and executes the program instructions to verify system security using the one or more pre-boot security components. The one or more pre-boot security components includes at least one identity verification component, e.g., a smart card, or a biometric sensor, e.g., a fingerprint sensor, a retinal scanner, and/or a voiceprint sensor, etc., and/or at least one system verification component, e.g., TPM, to query the system for system state information, and verify that the system has not been compromised.

Enhancing security of a system via access by an embedded controller to a secure storage device

A system and method for monitoring usage of peripheral devices and placing a second peripheral device in a low power state when the usage indicates that a second peripheral device is not being used. For example, if a computer system detects that a user's current typing rate indicates the user probably has both hands on a keyboard, the computer system may generate a signal to the computer mouse to enter a low power state. The computer system may use prior usage for a user to determine when current usage indicates that the second peripheral device is not being used. After the second peripheral device is placed in a low power state, the computer system may generate a signal to the second peripheral device to return to a normal power state when the computer system determines that the user no longer has both hands occupied.

Power management of computer peripheral devices which determines non-usage of a device through usage detection of other devices

A method and apparatus for configuration control and power management through special signaling is provided. In one embodiment, a computer system may include a processor and a plurality of devices that may act as a source device, a destination device, or both. A particular source device may be configured for communications with a destination device. The source device may further be configured to violate one or more known communications rules when communicating the with the destination device. The destination device may be configured to detect the violation. The violation of a known communications rule by the source device may indicate a pending change of state in the computer system, or that a change of state has occurred.

Method and apparatus for configuration control and power management through special signaling

A system may include a memory configured to store an attenuation waveform and control logic. The control logic is configured to receive a synchronizing signal indicative of an operating characteristic of a noise source. In response to a value of a characteristic (e.g., frequency) of the synchronizing signal, the control logic is configured to output the attenuation waveform from the memory if the attenuation waveform is associated with that value of the characteristic of the synchronizing signal. An attenuating noise generated dependent on the attenuation waveform attenuates a noise generated by the noise source.

Associative noise attenuation

A dedicated bus between a central processing unit and a peripheral unit, such as a graphics controller driving a video display, provides enhanced capability in an environment in which signal processing occurs within the central processing unit. The dedicated bus relieves other data buses, such as the PCI bus, of the need to communicate large amounts of data, such as decompressed video data. The resulting system supports high bandwidth transmissions of decompressed video data, enabling high resolution 24 bit full motion video and multiple data stream video.

Processor with decompressed video bus

An electronic system and method are presented for the implementation of functional redundancy checking (FRC) by comparing &ldquo;signatures&rdquo; produced by two different electronic devices, for example central processing units (CPUs). The signatures include a relatively small number of signals which reflect an internal state of each CPU. The electronic system includes a first and second CPU. Each CPU is configured to execute instructions and produce output signals. The first and second CPUs are preferably identical and execute instructions simultaneously such that their internal states and produced output signals should be the same at any given time. Each CPU includes a signature generator for generating the signature. The electronic system also includes a compare unit coupled to receive the signatures. The compare unit compares the signatures and produces an error signal if the signatures are not identical. The electronic system may be a computer system, further including a system bus and chip set logic. The system bus is adapted for coupling to one or more peripheral devices. The chip set logic is coupled between the first and second CPUs and the system bus, and functions as an interface between the first and second CPUs and the system bus. The first and second CPU are coupled to the chip set logic via separate processor buses. At least a portion of the signal lines of the separate processor buses are &ldquo;point-to-point&rdquo;, enabling the processor buses to achieve relatively high data transfer rates.

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Austin, TX, United States of America

Drew Jon Dutton