Sun Microsystems, Inc.

Oracle America, Inc.

Oracle International Corporation

Sanmina Corporation

Other

Drew George Doblar

Dawei Huang

Gabriel C Risk

Deqiang Song

Robert Cypher

Chung-Hsiao Wu

Han Y Ko

Dong Joon Yoon

Nirmal Chindhu Warke

Leo Yuan

Waseem Ahmad

Michael Bushue

Jianghui Su

Shinichi Iketani

Michael Stephen Harwood

Emrys John Williams

Jyh-Ming Jong

Zuxu Qin

Osman Javed

Stephen K Gee

Franz Michael Schuette

Trung T Nguyen

Brian L Smith

Jonathan E Starr

Jurgen M Schulz

Gin S Yee

David C Banks

Daniel R Cassiday

Chaim Nmi Amir

Prabhansu Chakrabarti

Andrew Keith Joy

Muthukumar Vairavan

Tai Quan

John C Schell

William Franklin Leven

Arif Al Amin

Michael J Bushue

Gurpreet S Dayal

William Joshua Price

Lam S Dong

William L Robertson

Baoqing Huang

Steven C Krow-Lucal

Jason H Bau

Matthew T Bowman

Daniel J Beckman

Teshager Tesfaye

Kin M Ho

Matthew J Tedone

Kenneth A Schmahl

Leandro A Chua, Jr

Paul Batcheller

Simon Dennis Forey

Juyoung Lee

Pruthvi A Chaudhari

Derek Shuntao Tsai

A multilayer printed circuit board is provided having a first conductive layer and a first plating resist selectively positioned within the first conductive layer. A second plating resist may be selectively positioned within a second conductive layer. A through hole extends through the first plating resist in the first conductive layer and the second plating resist in the second conductive layer. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

Simultaneous and selective wide gap partitioning of via structures using plating resist

A delay circuitry is configured to hold up power to a mass storage device after a power fault disables communication of the mass storage device with the host computer. The time delay is sufficient to allow saving of in-flight data from the storage device's volatile cache to the non-volatile media (of the storage device) and to update a metadata table in the non-volatile media.

Delay circuitry to hold up power to a mass storage device and method therefor

This disclosure describes systems and methods for determining a voltage margin (or margin) of a serializer/deserializer (SerDes) receiver in mission mode using a SerDes receiver. This is done by time-division multiplexing a margin determination and a tap weight adaptation onto the same hardware (or software, or combination of hardware and software). In other words, some parts of a SerDes receiver (e.g., an error slicer and an adaptation module) can be used for two different tasks at different times without degrading the effectiveness or bandwidth of the receiver. Hence, the disclosed systems and methods allow a SerDes receiver to determine the SerDes margin in mission mode and without any additional hardware or circuitry on the receiver chip.

Serial link voltage margin determination in mission mode

A non-transitory computer readable storage medium having computer readable program code embodied therein, where the computer readable program code is adapted to, when executed by a processor, implement a method for managing a power supply system. The method includes identifying a number of power supplies included in the power supply system, and determining a first system mode for the power supply system. The method also includes determining a first operating order for the power supplies, and assigning a first ACTIVE ON threshold to each of the power supplies to obtain a number of first ACTIVE ON thresholds. The method further includes assigning a first ACTIVE STANDBY OFF threshold to each of the power supplies to obtain a number of first ACTIVE STANDBY OFF thresholds, where the power supply system provides electrical power to at least one computer system.

Method for system energy use management of current shared power supplies

A system and method include a SerDes transmitter comprising a digital block operating in a digital voltage domain. The digital block can be configured to receive a first group of bits of data in parallel and store history bits from another group of data. The SerDes transmitter can further comprise an analog block operating in an analog voltage domain. The analog block can be configured to receive the first group of bits of data from the digital block, receive the history bits from the digital block, generate a plurality of combinations of bits with one or more bits from the first group of bits and zero or more bits from the history bits, align each combination of bits to a phase of a multi-phase clock; and input each combination into an output driver.

Power and area efficient SerDes transmitter

A method for reducing latency using a charging module when activating a power supply unit (PSU) among a plurality of PSUs in a power supply system. The method includes: Receiving, by the PSU from a power input feed, input power; receiving, from a supply bus shared by the plurality of PSUs, a first controlled signal designating a status of the PSU as standby; disabling, in response to the first controlled signal, a switching regulator of the PSU; receiving, from a voltage rail of the supply bus, charge flowing through a resistor of the charging module to maintain a charge of an output capacitor of the switching regulator; receiving a second controlled signal designating the status of the PSU as active; enabling the switching regulator; outputting a voltage from the PSU through the charging module to the voltage rail; and charging the output capacitor using the PSU.

Reducing latency when activating a power supply unit

A method for autonomous control by a power supply unit (PSU) among a number of current share PSUs in a power supply system. The method includes: Receiving input power from a power input feed; setting a mode of the PSU to ON; receiving a first controlled signal including a first number of IStar modes and thresholds; receiving a first activation signal activating IStar in the PSU; receiving a second controlled signal comprising a first voltage; determining that the first voltage is less than a first Active standby OFF threshold for an IStar mode of Active standby OFF; setting the IStar mode for the PSU to Active standby OFF; receiving a third controlled signal that includes a second voltage; determining that the second voltage is greater than a first Active ON threshold for an IStar mode of Active ON; and setting the IStar mode for the PSU to Active ON.

Autonomous control in current share power supplies

A feedback module is defined to receive as input a set of data sample signals and a set of reference sample signals. Each of the data and reference sample signals is generated by sampling a differential signal having been transmitted through a FIR filter. The feedback module is defined to operate a respective post cursor counter for each post cursor of the FIR filter and update the post cursor counters based on the received sets of data and reference sample signals. Also, the feedback module is defined to generate a tap weight adjustment signal for a given tap weight of the FIR filter when a magnitude of a post cursor counter corresponding to the given tap weight is greater than or equal to a threshold value. An adaptation module is defined to adapt a reference voltage used to generate the reference sample signals to a condition of the differential signal.

Real-time optimization of TX FIR filter for high-speed data communication

A method and apparatus for reducing the amplification of the duty cycle distortion of high frequency clock signals when is provided. A data signal is sent to a receiver via a first channel. A clock signal is sent to the receiver via a second channel. The clock signal is filtered to substantially remove therefrom low frequency components before the clock signal is used by the receiver to recover data from the data signal.

Method and system for reducing duty cycle distortion amplification in forwarded clocks

A method of implementing a low jitter and high bandwidth clock and data recovery (CDR) apparatus includes acquiring early, optimal, and late votes; determining which votes are allowed and weighted; disallowing votes not determined to as allowed; weighing votes, wherein votes that would make the CDR move to an extreme of a zero crossing are weighted less; and accumulating votes and adjusting a recovered clock phase based on the accumulated votes. A computer readable medium storing instructions to implement a low jitter and high bandwidth CDR apparatus, the instructions includes functionality to: acquiring early, optimal, and late votes; determining which votes are allowed and weighted; disallowing votes not determined to as allowed; weighing votes, wherein votes that would make the CDR move to an extreme of a zero crossing are weighted less; and accumulating votes and adjust recovered clock phase.

Low jitter and high bandwidth clock data recovery

A mechanism is provided for constructing an oversampled waveform for a set of incoming signals received by a receiver. In one implementation, the oversampled waveform is constructed by way of cooperation between the receiver and a waveform construction mechanism (WCM). The receiver receives the incoming signals, samples a subset of the incoming signals at a time, stores the subsets of sample values into a set of registers, and subsequently provides the subsets of sample values to the WCM. The WCM in turn sorts through the subsets of sample values, organizes them into proper orders, and 'stitches' them together to construct the oversampled waveform for the set of incoming signals. With proper cooperation between the receiver and the WCM, and with proper processing logic on the WCM, it is possible to construct the oversampled waveform for the incoming signals without requiring large amounts of resources on the receiver.

Mechanism for constructing an oversampled waveform for a set of signals received by a receiver

An analog baud rate clock and data recovery apparatus includes a first track and hold circuit that delays a received signal by one unit interval to create an odd signal; a second track and hold circuit that delays the received signal by one unit interval to create an even signal; a first comparator circuit; and a second comparator circuit. The first track and hold circuit outputs the odd signal to the first comparator circuit and the second comparator circuit. The second track and hold circuit outputs the even signal to the first comparator circuit and the second comparator circuit. The first comparator adds the odd signal to the even signal and outputs a first potential timing error. The second comparator subtracts the odd signal and the even signal and outputs a second potential timing error signal. A desired timing error signal is derived from the first and second potential timing error signals. The desired timing error signal is used to determine whether signal sampling is early or late.

Analog baud rate clock and data recovery

Various embodiments herein include one or more of systems, methods, software, and/or data structures to extract models of components (e.g., vias and traces) for PCB channels from measurements (or simulations) taken from physical PCB channels. By applying stochastic optimization to measurements of two PCB channels having different channel lengths, s-matrices (e.g., two-port, four-port, and the like) of the components of a PCB channel may be accurately determined by searching the multi-dimensional parameter space for parameters that comply with the measured values. Once the models for the components have been accurately determined, they may be utilized in constructing a model library that includes component models and is based on physical measurement data.

Extraction of component models from PCB channel scattering parameter data by stochastic optimization

A data communications system and methods are disclosed. The system includes a transmitter for conveying a data signal filtered by a finite impulse response (FIR) filter to a receiver via a channel. The receiver equalizes the received data signal using a decision feedback equalizer (DFE) and the FIR. The receiver samples the data signal to determine an error signal and uses the error signal to adapt settings of a pre-cursor tap coefficient of the FIR, one or more post-cursor tap coefficients of the FIR, a phase of the recovered clock, and a coefficient of the DFE. To adapt the settings, the receiver determines the error signal based on an error sample taken from the data signal in a single clock cycle. To determine an error signal, the receiver samples the data signal at a phase estimated to correspond to a peak amplitude of a pulse response of the channel.

Integrated equalization and CDR adaptation engine with single error monitor circuit

Growing community of inventors

San Jose, CA, United States of America

Drew George Doblar