Sonics, Incorporated

Facebook Technologies, LLC

Meta Platforms Technologies, LLC

Vakilotojar, Vida

Chou, Chien-chun

Swarbrick, Ian Andrew

Hamilton, Stephen W.

Wingard, Drew E.

Drew Eric Wingard

Chien-Chun Chou

Wolf-Dietrich Weber

Jay S Tomlinson

Stephen W Hamilton

Krishnan Srinivasan

Gregory Ehmann

Vida Vakilotojar

Geert Paul Rosseel

Lisa A Robinson

Ian A Swarbrick

Michael Jude Meyer

Nabil Masri

Thomas Wayne O'Connell

Glenn S Vinogradov

Timothy A Pontius

Alok Kumar Mathur

Jeremy Chan

Kevin L Daberkow

Kamil Synek

Valerio Catalano

Hervé Jacques Alexanian

Harutyun Aslanyan

Richard Aras

Jun Wang

Doddaballapur N Jayasimha

Neeraj Upasani

Wojciech Stefan Powiertowski

Neal Thomas Wingen

Miguel Angel Guerrero

Sridhar Gurumurthy Isukapalli Sharma

Marco Brambilla

Chien Chun Chou

Frank Seigneret

Pascal Chauvet

Ennio Salemi

Geert-Paul Rosseel

Minli Lin

Nabil N Masri

Thomas W O'Connell

Ruben Khazhakyan

Harutyan Aslanyan

Joseph Harwood

Sricharan Kasetti

Ian Andrew Swarbrick

Chein-Chun Chou

Chien Chum Chou

Michael Meyer

This disclosure describes various examples of a system which uses a multi-bank, multi-port shared memory system that may be implemented as part of a system on a chip. The shared memory system may have particular applicability in the context of an artificial reality system, and may be designed to have distributed or varied latency for one or more memory banks and/or one or more components or subsystems within the system on a chip. The described shared memory system may be logically a single entity, but physically may have multiple memory banks, each accessible by any of a number of components or subsystems. In some examples, the memory system may enable concurrent, common, and/or shared access to memory without requiring, in some situations, full locking or arbitration.

Artificial reality system having multi-bank, multi-port distributed shared memory

A system and method for accessing cache lines of an N-way set associative cache distributed across local memory of compute elements. The set associative cache includes a plurality of sets, with each location in cacheable local memory mapped to one of the sets and each set including N locations for caching data blocks read from the cacheable memory. Each set is mapped to one of the local memories, when that local memory is not in use by local compute elements. A cache controller is configured to receive a read request, to identify a data block in the cacheable memory associated with the address, to determine if the identified data block is in cache in one of the local memories, and, if the identified data block is in cache in one of the local memories, to fetch the identified data block from the cache.

Distributed temporal cache for Systems on a Chip

The disclosure describes techniques for interrupt and inter-processor communication (IPC) mechanisms that are shared among computer processors. For example, an artificial reality system includes a plurality of processors; an inter-processor communication (IPC) unit comprising a register, wherein the IPC unit is configured to: receive a memory access request from a first processor of the processors, wherein the memory access request includes information indicative of a hardware identifier (HWID) associated with the first processor; determine whether the HWID associated with the first processor matches an HWID for the register of the IPC unit; and permit, based on determining that the HWID associated with the first processor matches the HWID for the register of the IPC unit, the memory access request to indicate a communication from the first processor to at least one other processor.

Artificial reality system with inter-processor communication (IPC)

Methods, Apparatus, and Systems are discussed for a sequencer-based protocol adapter that executes a limited instruction set. The sequencer-based protocol adapter is implemented in electronic hardware and programmable registers in an integrated circuit and configured to transition a set of 1) one or more voltage sources, 2) one or more frequency sources, or 3) a combination of voltage sources and frequency sources, coupled with that sequencer-based protocol adapter. The sequencer-based protocol adapter manages power on the integrated circuit, via receiving a desired performance index at an input and then executing one or more of the limited instructions stored in the programmable registers in a proper sequence of steps in order to transition the coupled voltage sources and/or frequency sources from a current operational state to a desired operational state. Note, the desired operational state the coupled voltage sources and/or frequency sources corresponds to the received desired performance index.

Sequencer-based protocol adapter

In an embodiment, an operating point controller for two or more circuit regions in an integrated circuit is discussed. The OPC is configured to both i) set a resource state, including operating voltage and operating frequency, for each of those circuit regions, and ii) identify events to initiate transitions between two or more operating points for a given circuit region. The operating point controller is also configured to manage transitions between operating points for the two or more circuit regions on the integrated circuit. The operating point controller is a hardware based machine implemented in logic rather than software operating on a CPU processor.

Hardware-based operating point controller for circuit regions in an integrated circuit

In an embodiment, the OPC manages at least one of i) gating state and ii) different operating frequencies for a given circuit region. The operating point controller is configured to be capable of both 1) having sole control to set and manage the gating state and operating frequency for the given circuit region based on a first set of events, as well as 2) delegating control to a local power domain controller to set and manage i) gating state for components in that circuit region, ii) different operating frequencies for components in that circuit region, and iii) combinations of both, based on a second set of events, on a per operating point basis. The multiple operating points for that circuit region have different operating voltage levels and operating frequencies, and when delegated, the local power domain controller will chose the gating state and/or operating frequency.

Operating point controller for circuit regions

Flow logic supports concurrency of multiple threads and/or tag IDs to be concurrently communicated across the interconnect while allowing the one or more target IP cores to be able to reorder incoming request transactions from the initiator IP core in a manner that is optimal for that target IP core while relieving that target IP core from having to maintain the sequential issue order of transaction responses to the incoming request transactions in the thread or tags when processed by the target IP core. The flow logic cooperates with the reorder storage buffers to control an operation of the reorder storage buffers as well as control issuance of at least the request transactions from the initiator IP core onto the interconnect in order to maintain proper sequential ordering of the transaction responses for the thread or tags when the transaction responses are returned back to the initiator IP core.

Reordering responses in a high performance on-chip network

An arbitrator governs an arbitration between different power domains and sequences powering up the different power domains supplied by the same voltage supply (VS) circuit on the Chip. The arbitrator has sequencing logic that limits how many different power domains simultaneously power up to a maximum amount, which is less than enough instantaneous electrical current drawn on the VS-circuit to cause a reduction below a minimum allowable supply voltage level for the VS-circuit. The sequencing logic manages the sequencing of powering up the different power domains by factoring in i) whether different power domains arbitrating to power up are part of a set of power domains that share the VS-circuit, ii) an amount of an instantaneous electrical current drawn, and iii) an amount of credits available before the minimum allowable supply voltage level occurs for that VS-circuit. The sequencing logic controls a behavior of the power domains when powering up from multiple different behaviors.

Power manager with a power switch arbitrator

An interconnect for an integrated circuit communicating transactions between initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect is generally described. The interconnect routes the transactions between the target IP cores and initiator IP cores in the integrated circuit. A first aggregate target of the target IP cores includes two or more memory channels that are interleaved in an address space for the first aggregate target in the address map. Each memory channel is divided up in defined memory interleave segments and then interleaved with memory interleave segments from other memory channels. An address map is divided up into two or more regions. Each interleaved memory interleave segment is assigned to at least one of those regions and populates the address space for that region, and parameters associated with the regions and memory interleave segments are configurable.

Various methods and apparatus for configurable mapping of address regions onto one or more aggregate targets

A method, apparatus, and system are described, which generally relate to an integrated circuit having an interconnect that implements internal controls. The interconnect in an integrated circuit communicates transactions between initiator Intellectual Property (IP) cores and target IP cores coupled to the interconnect. The interconnect implements logic configured to support multiple transactions issued from a first initiator IP core to the multiple target IP cores while maintaining an expected execution order within the transactions. The logic supports a second transaction to be issued from the first initiator IP core to a second target IP core before a first transaction issued from the same first initiator IP core to a first target IP core has completed while ensuring that the first transaction completes before the second transaction and while ensuring an expected execution order within the first transaction and second transaction are maintained. The logic does not include any reorder buffering.

Various methods and apparatus to support outstanding requests to multiple targets while maintaining transaction ordering

Various methods and apparatus are described for communicating transactions between one or more initiator IP cores and one or more target IP cores coupled to an interconnect. A centralized Memory Management logic Unit (MMU) is located in the interconnect for virtualization and sharing of integrated circuit resources including target cores between the one or more initiator IP cores. A master translation look aside buffer (TLB) stores virtualization and sharing information in the entries of the master TLB. A set of two or more translation look aside buffers (TLBs) locally store virtualization and sharing information replicated from the master TLB. Logic in the MMU or other software updates the virtualization and sharing information replicated from the master TLB in the entries of one or more of the set of local TLBs.

Methods and apparatus for virtualization in an integrated circuit

A method, apparatus, and system are described, which generally relate to an interconnect routing transactions to target IP cores, including two or more channels making up a first aggregate target. The two or more channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores. The interconnect implements chopping logic to chop an individual transaction from a first initiator IP core whose address sequence crosses a channel address boundary from a first channel to a second channel within the first aggregate target into two or more burst transactions. A first chopped burst transaction is chopped to fit within the address boundaries of the first channel and a second chopped burst transaction is chopped to fit within the address boundaries of the second channel.

Various methods and apparatus to support transactions whose data address sequence within that transaction crosses an interleaved channel address boundary

A method, apparatus, and system in which an integrated circuit comprises an initiator Intellectual Property (IP) core, a target IP core, an interconnect, and a tag and thread logic. The target IP core may include a memory coupled to the initiator IP core. Additionally, the interconnect can allow the integrated circuit to communicate transactions between one or more initiator Intellectual Property (IP) cores and one or more target IP cores coupled to the interconnect. A tag and thread logic can be configured to concurrently perform per-thread and per-tag memory access scheduling within a thread and across multiple threads such that the tag and thread logic manages tags and threads to allow for per-tag and per-thread scheduling of memory accesses requests from the initiator IP core out of order from an initial issue order of the memory accesses requests from the initiator IP core.

Apparatus and methods to concurrently perform per-thread as well as per-tag memory access scheduling within a thread and across two or more threads

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Palo Alto, CA, United States of America

Drew Eric Wingard