Synopsys, Inc.

Synplicity, Inc.

Quicklogic Corporation

Drazen Borkovic

Kenneth S McElvain

Awartika Pandey

Andrew K Chan

Kevin K Yee

Mukesh T Lulla

Brian D Small

Atul Ahuja

Charles C Tralka

Roger Ang

Methods and apparatuses for circuit design are described. In one embodiment, the method comprises determining a distribution of nets of a circuit, the distribution of the nets comprising numbers of blocks that each of the nets has in each of a plurality of partitions of the circuit in a partitioning solution, moving a first block of the circuit from a source partition to a destination partition to modify the partitioning solution, and updating the distribution of the nets after the moving.

Circuit partitioning and trace assignment in circuit design

Methods and apparatuses to design and analyze digital circuits with time division multiplexing. In one embodiment, the method for designing a digital circuit comprises determining signal timing for a portion of the digital circuit, and automatically replacing nets for a plurality of connections in the digital circuit with a Time Division Multiplexing (TDM) channel in response to a determining of routing congestion.

Analysis of digital circuits with time division multiplexing

Methods and apparatuses to design and analyze digital circuits with time division multiplexing. At least one embodiment of the present invention efficiently models subsystems connected by a TDM channel by introducing equivalent delays in the connections for the subsystems, where the delays are determined according to the upper bounds of the delays caused by the TDM channel. The TDM channel is modeled with its equivalent delays. Thus, a transformation tool is allowed to take into account the original constraints and time budgeting of the sending subsystem and the receiving subsystem. The problem of asynchronous clock domains is eliminated; and, simulation time of the multiplexed circuit is also improved. In some embodiments of the present invention, multiple TDM slots are assigned to a particular signal to reduce the equivalent connection delay caused by the TDM channel for the particular signal.

Method and apparatus for the design and analysis of digital circuits with time division multiplexing

Methods and apparatuses for designing at least one integrated circuit (IC). In one embodiment, the method comprises partitioning a circuit into portions that represent a partitioning solution and assigning traces to interconnect the portions to generate a trace assignment solution. The method further comprises optimizing the circuit through a modification of at least one of the partitioning solution and the trace assignment solution, the optimizing based on evaluating a design parameter which is based at least in part on the trace assignment solution.

Methods and apparatuses for incremental circuit partitioning and incremental trace assignment. In one embodiment of the present invention, a cost function based on both the partitioning solution and the trace assignment solution is used for the partitioning of a circuit; in reducing the cost function, blocks of circuits are moved among partitions and the trace assignment are updated accordingly to evaluate the cost function. In one embodiment, the traces and nets are grouped according to the partitions they connect for trace assignment. In one embodiment, a flow diagram is constructed for assigning nets to traces; and, maximum flow algorithms are used. In one embodiment, a flow diagram includes feedthrough solutions, in which flow conservation is not preserved at certain nodes. In one embodiment, integer linear programming techniques are used for assigning nets to traces. In one embodiment, a distribution of nets, which defines the numbers of blocks that each net has in each partition, is computed and maintained for efficient determination of the number of nets in net groups.

Method and apparatus for circuit partitioning and trace assignment in circuit design

Methods and apparatuses to design a circuit. In one embodiment, the method includes determining a first multiplexing ratio by a computer. The method, in one embodiment, further includes determining, according to the first multiplexing ratio, a first partition solution of the circuit and a first trace assignment solution for nets crossing partition boundaries of the first partition solution of the circuit. In one embodiment, the first trace assignment solution time multiplexes signals for a first plurality of nets crossing partition boundaries of the first partition solution according to the first multiplexing ratio, the first trace assignment solution satisfying a trace constraint, the first partition solution satisfying an area constraint when circuitry for time multiplexing signals for the first plurality of nets is considered.

One embodiment of the present invention includes a technique for a gated clock conversion for a circuit which includes a gating circuit and a sequential element. The gating circuit has a gated clock net that drives a clock input of the sequential element. The sequential element receives a first input net at a data input and generates an output net. The gating circuit has a user-defined clock net. The technique includes determining the gating circuit and transforming the gating circuit to provide a second input net to the sequential element based on a cofactor condition of the gating circuit.

Reducing clock skew in clock gating circuits

Methods and apparatuses to design and analyze digital circuits with time division multiplexing. At least one embodiment of the present invention efficiently models subsystems connected by a TDM channel by introducing equivalent delays in the connections for the subsystems, where the delays are determined according to the upper bounds of the delays caused by the TDM channel. The TDM channel is modeled with its equivalent delays. Thus, a transformation tool is allowed to take into account the original constraints and time budgeting of the sending subsystem and the receiving subsystem. The problem of asynchronous clock domains is eliminated; and, simulation time of the multiplexed circuit is also improved. In some embodiments of the present invention, multiple TDM slots are assigned to a particular signal to reduce the equivalent connection delay caused by the TDM channel for the particular signal. In some embodiments of the present invention, timing simulation is performed using the equivalent delays to avoid the simulation of the TDM hardware; and, the simulation time step does not have to be reduced due to asynchronous clock, resulting in reduced simulation time.

A programmable device, such as a field programmable gate array, includes a main field that is programmable by the user and at least one embedded portion that is reserved to be programmed with a standard circuit design that is configured, for example, by the manufacturer. The embedded portion is similar to the main field, i.e., it has the same programmable structure, however, the embedded portion is not accessible to the user. In some embodiments, the embedded portion may be pre-programmed with the standard circuit design and in other embodiments the embedded portion is programmed while the user programs the main field. The programmable device may also include signature bits that are used by the programming unit to identify the programmable device as having the embedded portion and which standard circuit design to program into the embedded portion. The signature bit may be programmed after the manufacture of the programmable device or may be hard wired during the manufacture of the device. The programming unit recognizes the configuration of the signature bits and restricts access to embedded portion based on the configuration.

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Mountain View, CA, United States of America

Drazen Borkovic