Stmicroelectronics S.a.

Stmicroelectronics (rousset) Sas

Stmicroelectronics (alps) Sas

Stmicroelectronics (grand Ouest) Sas

Stmicroelectronics Design and Application S.r.o.

Dragos Davidescu

Jean-Francois Link

Sandrine Lendre

Vincent Onde

Olivier Ferrand

Loic Pallardy

Nicolas Anquet

Franck Roche

Ludovic Ruat

Jean Claude Bini

Jonathan Cottinet

Jean-François Link

Gosagan Padmanabhan

Igor Cesko

In an embodiment a system on chip includes a plurality of microprocessors, a plurality of slave resources, an interconnection circuit coupled between the microprocessors and the slave resources, the interconnection circuit configured to route transactions between the microprocessors and the slave resources and a processing controller configured to allow a user of the system to implement within the system at least one configuration diagram of the system defined by a set of configuration pieces of information used to define an assignment of at least one microprocessor to at least some of the slave resources, select the at least one microprocessors, and authorise an external debugging tool to access, for debugging purposes, only the slave resources assigned to the at least one microprocessor.

Method for managing the debugging of a system on chip forming for example a microcontroller, and corresponding system on chip

An embodiment system includes a first processor configured to process a suite of instructions and a second processor configured to process a subset of the suite of instructions. The system further includes a power management circuit configured to select the first processor or the second processor as a selected processor, the power management circuit being further configured to activate the selected processor or place the selected processor on standby. The system also includes a first peripheral device configured to generate a first interrupt signal, a switch configured to direct the first interrupt signal to the selected processor, and a first memory configured to store a first interrupt routine associated with the first interrupt signal, the selected processor being configured to execute the first interrupt routine in response to the first interrupt signal.

System and method for processing interrupts by processors of a microcontroller in a low-power mode

Several first digital streams of first digital samples at a first sampling frequency are processed to issue corresponding stream that are converted into second digital streams sampled at a second sampling frequency lower than said first sampling frequency. At least one delay to be applied to at least one first digital stream to satisfy a condition on the second digital streams is determined and applied to at least one first digital stream before converting. The converting operation performed is decimation filtering of the first digital streams. The application of the at least one delay to at least one first steam involves skipping a number of first digital samples in the at least one first digital stream. The number skipped depends on the value of the at least one delay. Samples that are skipped are not delivered for decimation filtering.

Method of processing digital signals, in particular digital acoustic signals, by sample skipping and decimation filtering and corresponding device

An apparatus having a microcontroller includes a processing unit, an internal communication bus assembly, a volatile memory, a non-volatile memory, a logic error management circuit, and two interface circuits. A first interface circuit couples the processing unit to the volatile memory via the internal communication bus assembly. A second interface circuit couples the processing unit to the non-volatile memory via the internal communication bus assembly. When the microcontroller is operating, the interface circuits are arranged to retrieve and evaluate requested data from their respective memory without intervention from the processing unit. In the event a failure is detected, the logic error management circuit is arranged to assert a stop signal. In some cases, detecting a failure includes comparing a check value stored in memory with a check value calculated from the data retrieved from memory.

MCU with processor-independent memory fault detection

A multifunctional timer/event counter device includes at least one counter controlled by a clock signal, and a control register including at least one binary number that will at least define a behavior of the counter. The device also includes a function module including at least one synchronization signal reception input and a reception input for at least one function control signal, the function module being capable of modifying the binary number as a function of at least the synchronization signal and the function control signal.

Multifunctional timer/event counter device and method of using such a device

The present invention relates to a method for managing the stack of a microprocessor comprising a central processing unit and a memory array, the central processing unit comprising registers containing contextual data and a stack pointer, the stack being a zone of the memory array used for saving contextual data upon a switch from a first to a second program. According to the present invention, the method comprises saving contextual data contained in a variable number of registers that varies according to the value of at least one flag stored in a register to be saved. Advantages: optimization of the filling of the stack and of the number of subprograms that can be interleaved.

Method for managing a microprocessor stack for saving contextual data

A system is provided for controlling access to protected data. The system includes storage means, protection means, an internal key, and means for receiving an input key from the outside. The storage means includes a protected zone for storing the protected data, and a command input for denying or authorising access to the protected data. The protection means controls access to the protected data by selectively activating the command input of the memory. The protection means authorises access to the protected data only when the internal key and the input key are identical. Also provided is a method for controlling access to protected data stored in a protected zone of a storage means. According to the method, an input key is received from the outside, and access to the protected data is authorised only when the input key and an internal are identical.

System and method for controlling access to protected data stored in a storage unit

An electronic device for storing protected data is disclosed. The electronic device includes memory protection logic operable to interface with memory, such as non-volatile ROM for storing protected data therein. The protected data in one embodiment is program code. The access to the protected data is restricted by a local processor, such as a microcontroller or microprocessor for execution thereon within the electronic device. Further, the electronic device includes validation logic operative in a first mode, for checking the validity of the data and for producing a validity signal, such as a checksum, enabled to determine whether that data is valid. In order to prevent access to intermediate validity calculations which may allow an individual to gain knowledge of the protected data, a validity signal output control is provided for inhibiting an output of the validity signal to outside the device until the validity of a predetermined quantity of the protected data has been checked. This predetermined quantity is made sufficiently large and preferably equal to all of the protected data. In another embodiment, a reset for setting the contents of the validity signal if the checking is interrupted is also included.

Device and method for protecting memory data against illicit access

A programmable clock generator delivers, using a primary clock signal of determined frequency, a first clock signal the frequency of which is equal to the frequency of the primary clock signal divided by a set point M. The set point M is a decimal number comprising a whole part Mand a decimal part Mand the clock generator modulates the period of the pulses of the first clock signal so that the duration of Ni successive pulses is substantially equal to M*Ni times the period of the primary clock signal, Ni being a reference number for modulating the period of the pulses of the first clock signal.

Decimal set point clock generator and application of this clock generator to UART circuit

An operational amplifier is provided that includes an inverting input channel, a non-inverting input channel, and an output stage. Each of the input channels controls at least one input transistor, and the output stage supplies an output voltage as a function of a potential difference at the input channels. Additionally, the operational amplifier includes at least one signal correction element in association with at least one of the input channels. The signal correction element is selectively put into circuit to selectively add an offset voltage correction signal to a signal that is supplied to the output stage in order to balance the characteristics of the two input channels. Also provided is a circuit for correcting the offset voltage of an operational amplifier. The circuit includes means for determining the output voltage of the operational amplifier, means for applying a reference voltage to one of the inputs of the operational amplifier, means for selectively coupling the inputs of the operational amplifier, and programming means for programming the placing of at least one signal correction element into circuit. Additionally, a method is provided for correcting the offset voltage of an operational amplifier in which an offset correction signal is determined by an iteration of cycles.

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Aix en Provence, France

Dragos Davidescu