Freescale Semiconductor,inc.

Nxp USA, Inc.

Dragos Adrian Badea

Petru Lauric

Bogdan Florin Ditu

Andrei Mihaila

Bogdan Batog

A mechanism is provided for debugging of system-wide packet loss issues in network devices by automatically identifying packet loss conditions at runtime of the network device and by logging and analyzing relevant data to help diagnose the issues resulting in lost packets. A network programmer defines a path through the communications processor that identified packets should follow, and then hardware mechanisms within the modules of the communications processor are used to determine whether the packets are indeed following the defined path. If not, then the hardware mechanisms halt processing and logging being performed by all or part of the communications processor and provide logged information and packet information to an analysis tool for display. In this manner, debugging information can be provided in real time, along with a history of the packet's progress through the communication processor stages.

Packet loss debug system and method

A method of generating an instrumented code from a program code executable on a programmable target is described. The method comprises analyzing the program code to detect a loop nest with regular memory access in the program code, providing a record of static memory address information associated with the loop nest, and instrumenting the program code to provide an instrumented code corresponding to the program code supplemented with an instrumentation instruction to output an information message comprising a dynamic memory address information field formatted to store a dynamic memory address information associated with the loop nest.

Method and system for generating a memory trace of a program code executable on a programmable target

A debug configuration tool for configuration of on-chip debug features comprises a database comprising predefined analysis points, each relating to a configurable chip entity, and comprising a configurable condition and a configurable action for the chip entity, a plurality of predefined analysis groups, each relating to a group of configurable chip entities, and comprising a configurable condition and a configurable action for the group of chip entities. The tool comprises a graphical user interface module arranged to display representations of at least some of the analysis points and the analysis groups on different levels of detail, and to receive input from a user to set the configurable conditions and/or actions for the displayed analysis points and the analysis groups. An application program interface module processes data received from the graphical user interface module to obtain debug settings and to communicate the debug settings to a debug target system configuration module.

Debug configuration tool with layered graphical user interface

The invention pertains to an optimization method for a compiler, comprising providing a model of inter-operand constraints of physical registers of a target-platform of a compilation; and a) providing an intermediate representation of a source code using virtual registers; b) grouping the virtual registers of the intermediate representation based on the model of inter-operand constraints into two or more groups, each group comprising at least one virtual register; c) if for at least one group at least one interference of virtual registers within the group occurs, amending the intermediate representation to resolve at least one interference and jumping to step b); otherwise d) providing a representation of a group interference graph of interferences between the groups; and e) allocating virtual registers to physical registers using a coloring scheme on the representation of the group interference graph. The invention also refers to a corresponding optimizer for a compiler and a computer-readable storage medium storing optimizing code.

Optimization method for compiler, optimizer for a compiler and storage medium storing optimizing code

A software pipelining method for generating a schedule for executing a plurality of instructions on a processor, the plurality of instructions involving one or more variables, the processor having one or more physical registers, the method comprising the step of scheduling each of the plurality of instructions, determining whether there is a variable for which there is less than a threshold number of physical registers to which that variable may be allocated, and unscheduling a currently scheduled instruction when there is a variable for which there is less than the threshold number of a physical registers to which that that variable may be allocated.

Growing community of inventors

Bucharest, Romania

Dragos Adrian Badea