Brilliance Semiconductor Inc.

Doung-Her Tsai

Chih-Hsien Wang

A refresh-free ultra-low power pseudo dynamic random access memory (DRAM). A clock that controls a DRAM is used to perform 1-bit read, 1-bit write, or a non-read and non-write operation. The clock includes a first read signal, a first write signal, or a first non-read and non-write signal. An interface circuit generates a second read signal, a second write signal, or a second non-read and non-write signal according to the first read signal, the first write signal, or the first non-read and non-write signal, respectively. A static random access memory (SRAM) cell is coupled with the interface circuit for performing the 1-bit read according to the second read signal, the 1-bit write according to the second write signal, or the non-read and non-write operation according to the non-read and non-write signal.

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Hsin-Chu, Taiwan

Doung-Her Tsai