Dell Products Inc.

Douglas Winterberg

Bhyrav M Mutnury

Wan-Ju Kuo

Stuart Allen Berke

V Mallikarjun Goud

A receiver includes an ODT network and a signal eye sampler. The ODT network terminates a data communication interface at a selectable impedance including a nominal impedance, at least one higher impedance, and at least one lower impedance. The signal eye sampler determines an eye margin for data received on the data communication interface. The receiver selects the nominal impedance, determines a nominal eye margin associated with the nominal impedance, selects a delta impedance from one of the higher impedance and the lower impedance, determines a delta eye margin associated with the delta impedance, determines whether the delta eye margin is greater than the nominal eye margin, and sets a run time impedance value for the data communication interface to the delta impedance when the delta eye margin is greater than the nominal eye margin.

On-die termination optimization

A printed circuit board (PCB), including: a ground reference layer; a pre-impregnated (pre-preg) layer having a surface; a first transmission line positioned on the surface; a second transmission line positioned on the surface spaced-apart from the first transmission line a first distance; and a solder mask layer positioned on the surface of the pre-preg layer and surrounding the first transmission line and the second transmission line, the solder mask layer having a thickness and a dielectric constant, wherein the thickness of the solder mask layer and a value of the dielectric constant of the solder mask layer cause convergence of electric fields associated with the first transmission line to be within a second distance from the first transmission line.

Reduction of crosstalk and impedance sensitivity for a microstrip in a printed circuit board of an information handling system

An information handling system includes a dual in-line memory module (DIMM) and a memory controller coupled to the DIMM via a data bus. The memory controller determines that a first lane of a byte group of the data bus is more susceptible to crosstalk than a second lane of the byte group, determines a first performance level of the first lane, changes a delay (D) of a third lane of the byte group, the third lane being adjacent to the first lane, and determines that a second performance level of the first lane is different from the first performance level in response to delaying the third lane.

DDR5 crosstalk mitigation through agressor misalignment

Managing performance at a memory subsystem, including: performing DFE at a memory subsystem based on an initial number of taps and an initial tap value range, the memory subsystem including memory modules and memory channels connecting respective memory modules; determining, based on the initial number of taps and the initial tap value range, a channel margin of a particular channel of the memory subsystem; disabling, at the particular channel, a tap; calculating, based on the disabled tap at the particular channel, a reduction in the channel margin of the particular channel; comparing the reduced channel margin of the particular channel to a margin threshold; determining, based on the comparing, that the reduced channel margin of the particular channel is greater than the margin threshold; in response to determining that the reduced channel margin of the channel is greater than the threshold, retaining the tap at the particular channel.

Managing decision feedback equalization at memory modules of an information handling system

An information handling system includes a memory controller and a dual in-line memory module (DIMM) coupled to the memory controller by a memory channel. The memory channel includes a plurality of single-ended multi-drop lanes arranged in a byte group. The information handling system determines, for each lane in the byte group, a tap setting for an associated decision feedback equalizer (DFE) of each lane. The information handling system further determines an average value for the tap settings for the lanes in the byte group, determines that a first tap setting for a first lane is different from the average value by greater than a threshold, and sets the first tap setting to the average value in response to determining that the first tap setting is different from the average value by greater than the threshold.

Enhanced decision feedback equalization for memory interfaces

An information handling system includes a control processing unit (CPU) including a dual in-line memory module (DIMM) controller and hosting a basic input output system (BIOS). A first and a second set of DIMMs are connected to the CPU through the DIMM controller and by a first communication channel and a second communication channel, respectively. Each DIMM in the first and second set of DIMMs may be configured by the BIOS to include a unique data bus IO voltage (V) setting for bidirectional communications with the CPU.

System and method for variable input output voltage on different channels for increasing power efficiency

A method includes modeling a design of a memory channel to provide a plurality of transfer functions associated with the design and multiplying an input spectrum with each of the transfer functions to provide a plurality of results. The method further includes summing the results to provide an output spectrum for the design, performing an inverse Fast Fourier Transform (FFT) on the output spectrum to provide an output signal for the design, and determining a bit error rate (BER) for the design based on the output signal.

System and method for simulating a memory technology

A circuit board includes first and second lines of surface mount pads, and a trace. The surface mount pads within the first line extend from a first edge of the circuit board toward a second edge of the circuit board. The surface mount pads within the second line extend from the first edge of the circuit board toward the second edge of the circuit board, and the surface mount pads within the second line are further from a third edge of the circuit board as compared to the surface mount pads within the first line. The trace is located on a top surface of the circuit board, and extends from the third edge to a fourth edge of the circuit board. The spacing between first adjacent surface mount pads within the first line enables the trace to be routed between the first adjacent surface mount pads with less crosstalk between signals on the trace and signals on the surface mount pads within the first line.

Surface mount connector pad

In accordance with embodiments of the present disclosure, a system may include a driver, a plurality of drops, and a plurality of transmission lines, including one transmission line between the driver and one of the plurality of drops and one transmission line between successive adjacent drops. Each particular transmission line of the plurality of transmission lines may be manufactured to have a desired impedance based on a corresponding effective impedance as seen at a drop located on an end of the particular transmission line furthest from the driver in a direction away from the driver.

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Austin, TX, United States of America

Douglas Winterberg