International Business Machines Corporation

Infineon Technologies Ag

Douglas Wayne Kemerer

Stephen Gerard Shuma

Mark Steven Styduhar

Oscar Conrad Strohacker

Corey Kenneth Barrows

Douglas Willard Stout

Paul Steven Zuchowski

Lijiang L Wang

Peter Albert Twombly

Ronald A Piro

Edward W Seibert

Elliot L Gould

Lance A McAllister

Deborah A Wellburn

Guy R Richardson

David James Hathaway

Kenneth Joseph Goodnow

William John Livingstone

Daniel Joseph Mainiero

Joseph Leonard Metz

William R Tonti

Dureseti Chidambarrao

John Atkinson Fifield

Michael Richard Ouellette

John Edward Barth, Jr

Hans-Joachim Barth

Stephen Edward Greco

Gustavo Enrique Tellez

Darren Lane Anand

Steven Frederick Oakland

David E Lackey

Daniel Nelson Maynard

Henry Atkinson Nye, Iii

Patrick H Buffet

Timothy W Budell

Tina Jane Wagner

Pamela Sue Gillis

Thomas R Bednar

Henry A Bonges, Iii

Lloyd G Burrell

Joseph L Chan

Alain Caron

James V Crain, Jr

Emmanuel F Crabbe

Peter O Jakobsen

Eric Jasinski

Donald S Kent

David K Anderson

Esmaeil Rahmati

Albrik Avanessian

Peter A Twembly

Paul S Zuchewski

Douglas W Sinut

Peter S Wissell

Jeannie Therese Harrigan Panner

Jeannie Therese Panner

A method comprises tracing a first and second terminal of a junction through a circuit layout to associated power supplies to determine their respective defined bias values. The method further comprises comparing the defined bias values of each terminal in order to determine, based on the comparison, whether the junction is forward biased.

Identifying parasitic diode(s) in an integrated circuit physical design

A design rule that determines a degree of overlap between two design elements in two adjoining levels by estimating a physical overlap area, or an 'intersect area,' of corresponding structures in a semiconductor chip is provided. The estimation of the physical intersect area may factor in line edge biasing, critical dimension tolerance, overlay tolerance, and corner rounding to provide an accurate estimate of a physical area for each of the structures corresponding to the two design elements. The intersect area is employed as a metric to determine compliance with a ground rule, i.e., the ground rule is specified in terms of the intersect region. Other derived quantities such as electrical resistance, electromigration resistance, expected yield may be calculated from the intersect area, and may be advantageously employed to optimize the design data.

Intersect area based ground rule for semiconductor design

The embodiments of the invention provide a design structure for detection and compensation of negative bias temperature instability (NBTI) induced threshold degradation. A semiconductor device is provided comprising at least one stress device having a voltage applied to its gate node and at least one reference device having a zero gate-to-source voltage. A controller is also provided to configure node voltages of the device and/or the reference device to reflect different regions of device operations found in digital and analog circuit applications. Moreover, the controller measures a difference in current between the stress device and the reference device to determine whether NBTI induced threshold degradation has occurred in the stress device. The controller also adjusts an output power supply voltage of the stress device until a performance of the stress device matches a performance of the reference device to account for the NBTI induced threshold degradation.

Mechanism for detection and compensation of NBTI induced threshold degradation

A design structure. The design structure includes: a first set of FETs having a designed first Vt and a second set of FETs having a designed second Vt, the first Vt different from the second Vt; a first monitor circuit containing at least one FET of the first set of FETs and a second monitor circuit containing at least one FET of the second set of FETs; a compare circuit configured to generate a compare signal based on a performance measurement of the first monitor circuit and of the second monitor circuit; a control unit responsive to the compare signal and configured to generate a control signal regulator based on the compare signal; and an adjustable voltage regulator responsive to the control signal and configured to voltage bias wells of FETs of the second set of FETs, the value of the voltage bias applied based on the control signal.

Methods and circuits to reduce threshold voltage tolerance and skew in multi-threshold voltage applications

A circuit and a method for adjusting the performance of an integrated circuit, the method includes: comprising: (a) measuring the performance of a first monitor circuit having at least one field effect transistor (FET) of a first set of FETs, each FET of the first set of FETs having a designed first threshold voltage; (b) measuring the performance of a second monitor circuit having at least one field effect transistor (FET) of a second set of FETs, each FET of the second set of FETs having a designed second threshold voltage, the second threshold voltage different from the first threshold voltage; and (c) applying a bias voltage to wells of the FETs of the second set of FETs based on comparing a measured performance of the first and second monitor circuits to specified performances of the first and second monitor circuits.

Methods to reduce threshold voltage tolerance and skew in multi-threshold voltage applications

Disclosed herein is a system for controlling power supply voltage to an on-chip power distribution network. The system incorporates a programmable on-chip sensing network that can be selectively connected to the power distribution network at multiple locations. When the sensing network is selectively connected to the power distribution network at an optimal sensing point, a local voltage feedback signal from that optimal sensing point is generated and used to adjust the power supply voltage and, thus, to manage voltage distribution across the power distribution network. Additionally, the system incorporates a policy for managing the voltage distribution across the power distribution network, a means for profiling voltage drops across the power distribution network and a means for selecting the optimal sensing point based on the policy and the profile. Another embodiment of the system can further control power supply voltages to multiple power distribution networks on the same chip.

Programmable on-chip sense line

The embodiments of the invention provide an apparatus and method for detection and compensation of negative bias temperature instability (NBTI) induced threshold degradation. A semiconductor device is provided comprising at least one stress device having a voltage applied to its gate node and at least one reference device having a zero gate-to-source voltage. A controller is also provided to configure node voltages of the device and/or the reference device to reflect different regions of device operations found in digital and analog circuit applications. Moreover, the controller measures a difference in current between the stress device and the reference device to determine whether NBTI induced threshold degradation has occurred in the stress device. The controller also adjusts an output power supply voltage of the stress device until a performance of the stress device matches a performance of the reference device to account for the NBTI induced threshold degradation.

A circuit and a method for adjusting the performance of an integrated circuit, the circuit includes: first and second sets of FETs having respective first and second threshold voltages, the first threshold voltage different from the second threshold voltage; a first monitor circuit containing at least one FET of the first set of FETs and a second monitor circuit containing at least one FET of the second set of FETs; a compare circuit adapted to generate a compare signal based on a performance measurement of the first monitor circuit and a performance measurement of the second monitor circuit; and a control unit adapted to generate a control signal to a voltage regulator based on the compare signal, the voltage regulator adapted to supply a bias voltage to wells of FETs of the second set of FETs, the value of the bias voltage based on the control signal.

Circuits to reduce threshold voltage tolerance and skew in multi-threshold voltage applications

An integrated circuit chip having a contact layer that includes a plurality of Vdd, Vddx, ground and I/O contacts arranged in a generally radial pattern having diagonal and major axis symmetry and generally defining four quadrants. A multilayer X-Y power grid is located beneath the contact layer. A wiring layer is interposed between the contact layer and power grid to provide a well-behaved electrical transition between the generally radial Vdd, Vddx and ground contacts and the rectangular X-Y power grid. The interposed wiring layer includes concentric square rings of Vdd, Vddx and ground wires located alternatingly with one another. The Vddx wires are discontinuous between adjacent quadrants so that the magnitude of Vddx may be different in each quadrant of the chip if desired.

Integrated circuit chip having a ringed wiring layer interposed between a contact layer and a wiring grid

A method and a system for improving manufacturing productivity of an integrated circuit. The method including: (a) generating a set of physical design rules, (b) assigning a rule scoring equation to each physical design rule of the set of physical design rules; (c) checking a physical design of the integrated circuit for deviations from each design rule; (d) computing a score for each physical design rule, using the corresponding rule scoring equation assigned to each physical design rule, for which one or more deviations were found in step (c); and (e) computing a productivity score for the integrated circuit design based on the scores computed in step (d).

Method and system for improving integrated circuit manufacturing productivity

A semiconductor device () having support structures () beneath wirebond regions () of contact pads () and a method of forming same. Low modulus dielectric layers () are disposed over a workpiece (). Support structures () are formed in the low modulus dielectric layers (), and support vias () are formed between the support structures (). A high modulus dielectric film () is disposed between each low modulus dielectric layer (), and a high modulus dielectric layer () is disposed over the top low modulus dielectric layer (). Contact pads () are formed in the high modulus dielectric layer (). Each support via () within the low modulus dielectric layer () resides directly above a support via () in the underlying low modulus dielectric layer (), to form a plurality of via support stacks within the low modulus dielectric layers ().

Support structures for wirebond regions of contact pads over low modulus materials

A method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox allows a reduction in the number of fuses required to repair or customize an integrated circuit and allows fuses to be grouped outside of the macros repaired by the fuses. The remote location of fuses allows flexibility in the placement of macros having redundant repair capability, as well as a preferable grouping of fuses for both programming convenience and circuit layout facilitation. The fuses are arranged in rows and columns and represent control words and run-length compressed data to provide a greater quantity of repair points per fuse. The data can be loaded serially into shift registers and shifted to the macro locations to control the selection of redundant circuits to repair integrated circuits having defects or to customize logic.

Method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox

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Essex Junction, VT, United States of America

Douglas Wayne Kemerer