International Business Machines Corporation

Other

Douglas W Westcott

Jeffrey Mark Nick

David Harold Surman

Thomas Anthony Gregg

Gregory Salyer

Dennis J Dahlen

Neil G Bartow

David Arlen Elko

Robert S Capowski

Louis T Fasano

Steven N Goss

Ruth A Allen

Mark A Brooks

Gerald A Maley

William John Starke

Eric M Schwarz

Casper A Scalzi

Michael J Jordan

Wendell W Wilkinson

Patrick John Sugrue

Paul J Brown

Richard Dievendorff

James H Warnes

James R Urquhart

Dermot Flaherty

Daniel Francis Casper

Georgette L Kurdt

Kelly B Pushong

Robert A Pascoe

Kenneth J Fredericks

Steven Bruce Jones

Vincent P Zeyak, Jr

Charles N Sprott

Paul W Jones

Raymond H Warren

Valerie White

Various enhancements are made to the architecture of a list processor to facilitate its use in implementing a message queue that is shared by queue managers residing across a multisystem complex. A new list structure control&#x2014;a program list entry identifier indicator, or PLEIDI&#x2014;is defined to allow the user to specify whether user-defined entry IDs are used when the list is allocated. A new delete list (DL) command is added that sequentially processes list entries in the order in which they exist on the specified list. A new move list entries (MLES) command provides a performance-optimized means to process an input list of entries. New key comparison functions and list monitoring enhancements have also been added. A new type of key called a secondary list entry key (SLEK) allows the user to specify a secondary key value as a means to identify a list entry.

Method and apparatus for processing a list structure

A method and apparatus for implementing a shared message queue using a list structure. A put list is defined comprising a sequence of list entries, each of which corresponds to a message in the queue and has an associated list entry key. Each list entry key corresponding to an uncommitted message falls within an uncommitted key range defining an uncommitted portion of the put list, while each list entry key corresponding to a committed message falls within a committed key range defining a committed portion of the put list. To write a message to the queue, a list entry is added to the put list having a list entry key within the uncommitted key range.

Method and apparatus for implementing a shared message queue using a list structure

A coupling facility is coupled to one or more other coupling facilities via one or more peer links. The coupling of the facilities enables various functions to be supported, including the duplexing of structures of the coupling facilities. Duplexing is performed on a structure basis, and thus, a coupling facility may include duplexed structures, as well as non-duplexed or simplexed structures.

Synchronizing processing of commands invoked against duplexed coupling facility structures

Method, system and program products for resolving potential deadlocks

Storage structures of a shared storage processor of a computing environment are copied. A copy operation for a storage structure of the shared storage processor is initiated. Although the storage structure is owned by an exploiter of the storage structure, at least a portion of the contents of the storage structure is copied via an operating system of the computing environment. The at least a portion of the contents are copied from the storage structure to another storage structure of the computing environment. Both storage structures may be located within the same shared storage processor or within different shared storage processors.

Method, system and program products for copying coupling facility structures

Lock structures of a shared storage processor of a computing environment are copied. A copy operation for a lock structure of the shared storage processor is initiated. Although the lock structure is owned by an exploiter of the lock structure, one or more objects of the lock structure are copied via an operating system of the computing environment. The one or more objects are copied from the lock structure to another lock structure of the computing environment. Both lock structures may be located within the same shared storage processor or within different shared storage processors.

Method, system and program products for copying coupling facility lock structures

List structures of a shared storage processor of a computing environment are copied. A copy operation for a list structure of the shared storage processor is initiated. Although the list structure is owned by an exploiter of the list structure, one or more objects of the list structure are copied via an operating system of the computing environment. The one or more objects are copied from the list structure to another list structure of the computing environment. Both list structures may be located within the same shared storage processor or within different shared storage processors.

Method, system and program products for copying coupling facility list structures

A lock structure, which includes many entries, is partitioned into segments. A number of the segments are cleaned up in parallel, such that cleanup processing of the entire lock structure is optimized. The lock structure is maintained within a coupling facility, which provides access to the lock structure by one or more processors coupled to the coupling facility. The cleaning up of the lock structure is performed by commands driven by the one or more processors and executed within the coupling facility.

System of performing parallel cleanup of segments of a lock structure located within a coupling facility

Performing parallel cleanup of segments of a lock structure

Method of performing parallel cleanup of segments of a lock structure

Preprocessing emulation methods utilizing search argument controls for a template routine address table in a target computing system. Target routines are stored in a target computing system for emulating incompatible instructions of an incompatible architecture which need not be recognized by the architecture of the target computing system. Preprocessing of template routines is preferrably executed on an Auxiliary Emulation Processor (AEP) which may access and patch (modify) some or all of the target instructions in any selected target routine and send them through a queue to a target processor for execution. Execution of the target routines on a target processor emulates the execution of incompatible instructions in an incompatible program in the incompatible architecture. The target processor feeds back results from the execution of target routines to modify any search argument being generated for a currently accessed incompatible instruction to allow the preprocessing selection among multiple target routines for any incompatible instruction currently executing on the target processor to represent any mode or state set by for the incompatible instruction. Another type of feed back from a currently executing target template routine enables non-sequential virtual addressing selection by the preprocessor's access of incompatible instructions during execution of the incompatible program to support incompatible instruction branches and incompatible authority controls. End routine controls are provided in the template routines for feedback synchronization of the accessing of each next incompatible instruction with execution results of each current incompatible instruction having its tempate routine currently executed by the target processor.

Preprocessing of stored target routines for controlling emulation of

Provides a program translation and execution method which stores target routines (for execution by a target processor) corresponding to incompatible instructions, interruptions and authorizations of an incompatible program written for execution on another computer system built to a computer architecture incompatible with the architecture of the target processor's computer system. The disclosed process allows the target processor to emulate incompatible acts expected in the operation of an incompatible program when the target processor itself is incapable of performing the emulated acts. Each of the instructions, interruptions and authorizations found in the incompatible programs has one or more corresponding target routines, any of which may need to be preprocessed before it can precisely emulate the execution results required by the incompatible architecture. Target routines (corresponding to the incompatible instruction instances in an incompatible program being emulated) are accessed, patched where necessary, and executed by a target processor to enable the target processor to precisely obtain the execution results of the emulated incompatible program. Before preprocessing, each target routine may not be able to provide identical execution results as required by the incompatible architecture, and the preprocessing may patch one or more of its target instructions to enable the target routine to perform the identical emulation execution of the corresponding incompatible instruction. The patching and other modifications to a target routine are done by one or more preprocessing instructions stored in the target routine.

Preprocessing of stored target routines for emulating incompatible

A system for resetting a cache in a first device connected by a multilinelink to a memory in a second device. A transceiver in the first element connects to one end of each of the link lines and a transceiver in the second device connects to the other end. The transmitter in the first device transceiver is disabled in response to a failure of the transceiver to receive messages from the second device. The transmitter in the first device transceiver also selectively sends a reset sequence to the receiver in the second device. A detector detects when all of the receivers in the second device have either received a reset sequence or have detected that a transmitter in the first device is disabled. The detector sets a latch in response, representing that data in the second device cache is invalid. Optionally, the second device has responders which send responses over the link lines indicating receipt of a reset sequence. The transmitters in the first device switch to a disabled state when the responses are not received within a specified period.

Interconnect failure detection and cache reset apparatus

A system for the transmission of information between elements of a data processing complex and a method for establishing such a system. Two elements of a data processing system are connected by a physical link comprising multiple conductors attached to transceivers at channels in each data processing element. Once the transceivers have been synchronized, commands and responses are exchanged which ensure that all of the transceivers in a channel are connected to the same channel on the other end of the conductor. If the transceivers are considered configured and an entry is made in a Configured-Transceiver table. A search is made of an Allowed-Operational-Link table which contains sets of transceivers which are allowed to become operational links. The set of transceivers thus found, is compared against the Configured-Transceiver-Table to verify that all of the members of the set have been configured. If a match is fondled, this set of transceivers becomes an Intended-Operational-Link. The Intended-Operational-Link is verified to ensure that both channels agree on the set of conductors will form the operational link. If the Intended-Operational-Link verifies, the operational link is established therefrom. The link can be reconfigured by utilizing a quiesce function.

Allowed operational-link transceiver table verifies the operational

A system for the transmission of information between elements of a data processing complex and a method for establishing such a system. Two elements of a data processing system are connected by a physical link comprising multiple conductors attached to transceivers at channels in each data processing element. Once the transceivers have been synchronized, commands and responses are exchanged which ensure that all of the transceivers in a channel are connected to the same channel on the other end of the conductor. If the transceivers are considered configured an entry is made in a Configured-Transceiver table. A search is made of an Allowed-Operational-Link table which contains sets of transceivers which are allowed to become operational links. The set of transceivers thus found, is compared against the Configured-Transceiver-Table to verify that all of the members of the set have been configured. If a match is found, this set of transceivers becomes an Intended-Operational-Link. The Intended-Operational-Link is verified to ensure that both channels agree on the set of conductors will form the operational link. If the Intended-Operational-Link verifies, the operational link is established therefrom. Pacing information is exchanged on the link causing null words to be inserted at an optimum rate to compensate for slow receivers.

Null words for pacing serial links to driver and receiver speeds

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Rhinebeck, NY, United States of America

Douglas W Westcott