Motorola Corporation

Csr Technology Inc.

Douglas W Schucker

Walter C Seelbach

Noshir Behli Dubash

Jeffrey J Ogren

Thomas Michael King

Gregory Djaja

Ronald Clayton Alford

Jeffrey Koeller

Frederic B Shapiro

Peter Naji

Richard J Swindlehurst

Shi-Chuan Lee

Timothy J Jennings

Patrick T Hickman

Francis Casey

Greg Djaja

Lee Mah

Siva Bonasu

David B Weaver

Pat Hickman

Jarvis Tou

Systems and methods for mitigating multipath signals in a receiver are provided. In this regard, a representative system, among others, includes a radio frequency (RF) front-end and at least one analog-to-digital converter (ADC). The RF front-end receives FM signals and down-converts the received frequency signals to intermediate frequency (IF) signals. The analog-to-digital converter (ADC) receives the intermediate frequency signals and digitizes multiple FM channels around a desired FM channel associated with the down-converted signals. The system further includes multiple sets of digital processing components that are configured to simultaneously receive and process the digitized multiple channels. The multiple sets of digital processing components include at least two parallel channel selection and demodulation paths in which the respective digitized multiple channels are processed therethrough.

Systems and methods for digitizing multiple channels in a receiver

Systems and methods for channel pairing a transmitter and a receiver are provided. In this regard, a representative method, among others, includes selecting a channel in a radio frequency (RF) band; transmitting a carrier and alert tone on the selected channel in the RF band; responsive to detecting the transmitted carrier and alert tone, demodulating the carrier and alert tone on the selected channel in the RF band and producing the demodulated alert tone; and responsive to detecting the produced alert tone, using the selected channel to establish a wireless link between the transmitter and receiver.

Systems and methods for channel pairing a transmitter and a receiver

A monolithic wireless receiver suitable for use in a global positioning system (GPS) or other radio frequency (RF) application suitably includes a mixed-mode integrated circuit and a stacked memory device. The mixed mode integrated circuit appropriately includes a digital portion and an analog portion on a common die. The analog portion implements an RF receiver circuit, and the digital portion includes a signal processor that communicates with the RF receiver. The memory device appropriately communicates with the integrated circuit to store electronic instructions and data for the signal processor. The monolithic receiver may be conveniently integrated into a portable electronics device such as a camera, personal digital assistant (PDA), portable phone or the like to provide location sensing or other RF functionality.

Wireless receiver with stacked, single chip architecture

A global position system (GPS) receiver for a host product is controlled by a microcontroller that also controls other functions in the host product. The GPS receiver includes an RF downconverter and a digital signal processor. The digital signal processor includes a correlator and an interface for asynchronously interfacing the correlator with the product's microcontroller. A monolithic integrated circuit includes RF downconverter circuitry, the correlator, and the interface for the GPS receiver.

Host-independent monolithic integrated circuit for RF downconversion and digital signal processing of GPS signals

A method for obtaining characterization of timing parameters of a sequential circuit includes inputting predetermined data sequences to the sequential circuit. The sequential circuit is then simulated in response to the predetermined data sequences, and signals appearing at internal nodes of the sequential circuit are observed with respect to time. A plurality of timing parameters of the sequential circuit can then be calculated by using the values of the signals at the internal nodes.

Simulation of sequential circuits for calculating timing characteristics

A voltage level translator circuit converts an input signal referenced between first and second operating potentials to an output signal referenced between second and third operating potentials. The input signal is level shifted through cascoded transistors and latched by series inverters to drive upper cascoded transistors in the output stage. The input signal is delayed before driving lower cascoded transistors in the output stage. The output stage transistors are cascoded in a similar manner as the level shifting section. The logic state of the input signal determines whether the upper cascoded transistors or the lower cascoded transistors in the output stage are activated to set the logic state of the output signal of the voltage level translator circuit. Additional cascoded transistors may be stacked to extend the range of voltage translation. The voltage level translator circuit is applicable to sub-micron technology.

Voltage level translator circuit with cascoded output transistors

A method for optimization of delay times in a digital circuit. The method comprises selecting a logic gate (12), and constructing a model (35) which predicts the delay time (27) of the logic gate (12). Varying the parameters which control the model to more accurately predict the delay time (48). Summing the delay time (48) due to each logic gate (12) which comprises the signal path. Repeating the method for each signal path within the digital circuit until all signal paths are computed. Modifying the digital circuit based on the calculated delay times (48) so as to better satisfy a predetermined measurement criteria.

Method for optimization of digital circuit delays

A block architected integrated circuit having a predetermined power and signal grid structures is provided. The integrated circuit includes a plurality of function blocks such as firm function blocks, standard cell logic blocks, and gate array logic blocks which are all designed according to the power and signal grid structures of the integrated circuit and from standard library elements of the base cell array. These function blocks have full floating capability with respect to the granularity of the power and signal grid structures. The integrated circuit also includes one or more hard function blocks which are not designed according to the power or signal grid structures of the integrated circuit. Further, the integrated circuit may also include one or more blocks which are designed from a different technology than the base cell array of the integrated circuit and, thus are also not designed according to the power or signal grid structures of the integrated circuit. As a result, these blocks must be adapted to readily fit within the power and signal grid structures of the integrated circuit. However, once adapted, these blocks also have full floating capability with respect to the granularity of the power and signal grid structures.

Firm function block for a programmable block architected heterogeneous

A block architected integrated circuit having predetermined power and signal grid structures is provided. The integrated circuit includes a plurality of function blocks such as firm function blocks, standard cell logic blocks, and gate array logic blocks which are all designed according to the power and signal grid structures of the integrated circuit and from standard library elements of the base cell array. These function blocks have full floating capability with respect to the granularity of the power and signal grid structures. The integrated circuit also includes one or more hard function blocks which are not designed according to the power or signal grid structures of the integrated circuit. Further, the integrated circuit may also include one or more blocks which are designed from a different technology than the base cell array of the integrated circuit and, thus are also not designed according to the power or signal grid structures of the integrated circuit. As a result, these blocks must be adapted to readily fit within the power and signal grid structures of the integrated circuit. However, once adapted, these blocks also have full floating capability with respect to the granularity of the power and signal grid structures.

Programmable block architected heterogeneous integrated circuit

A source terminated transmission line driver circuit having an output coupled to a transmission line through a resistor is provided. The driver circuit has a gate circuit for providing first and second signals and a pulse generator circuit responsive to the second signal of the gate circuit for providing a pulse current at an output when the second signal is switching from a first logic state to a second logic state and for otherwise providing a quiescent current at the output. The driver circuit also has a first circuit responsive to the first output signal of the gate circuit for sourcing current to the output of the source terminated transmission line driver circuit, the first circuit being responsive to the second output signal of the gate circuit for sinking an adjustable current at the output of the source terminated transmission line driver circuit. The first circuit has a first transistor having a collector, a base and an emitter, the emitter being coupled to the output of the source terminated transmission line driver circuit, the base being coupled to receive the first signal of the gate circuit, and the collector being coupled to the first supply voltage terminal, a second transistor having a collector, a base and an emitter, the emitter of the second transistor being coupled to the output of the source terminated transmission line driver circuit, the base of the second transistor being coupled to the output of the pulse generator circuit, the collector being coupled to a second supply voltage terminal, a third transistor having a collector, a base and an emitter, the collector of the third transistor being coupled to the first supply voltage terminal, the base of the third transistor being coupled to the base of the first transistor, and a fourth transistor having a collector, a base and an emitter, the collector and base of the fourth transistor being coupled to the emitter of the third transitor, the emitter of the fourth transistor being coupled to the base of the second transistor.

Source terminated transmission line driver

An external contact method and package wherein one embodiment includes a semiconductor die having a plurality of metallization layers including a top metallization layer that is covered by a passivating layer. At least a portion of the passivating layer is removed to expose at least a portion of the top metallization layer. Once the top metallization layer is exposed, external contact means are press-fit directly into the exposed portion. In a high powered ECL circuit, the present invention eliminates or greatly decreases voltage drop problems along the power bus lines which cause logic errors if the voltage drop is too large.

Direct contact TAB method

An ECL transient driver discharges a capacitive load at the output of an emitter follower with a pulse whose amplitude and duration is determined by the charge on the load. A pull-up transistor is coupled to an output terminal for selectively supplying a voltage thereto in response to a first signal from a logic circuit. A pull-down transistor is coupled to the output terminal for selectively sinking a current therefrom in response to a second signal. A comparator circuit is coupled to the pull-down transistor, the logic circuit, and the output terminal, for selectively providing the second signal in response to the first signal and an output voltage on the output terminal.

Load controlled ECL transient driver

A BI-CMOS circuit is provided wherein an output terminal is coupled between an upper and lower NPN push-pull transistor. This provides high current drive capability along with no d.c. power dissipation. A P-channel device has a source and a drain connected to the collector and base, respectively, of the upper NPN transistor. An N-channel device has a source and drain connected to the base and collector, respectively, of the lower NPN transistor. The gates of the P-channel and N-channel devices are connected to an input terminal and provide a high impedance thereat. Additional N-channel devices are coupled between the bases of the upper and lower NPN transistors and a supply voltage terminal for improving the switching speed of the output signal.

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Mesa, AZ, United States of America

Douglas W Schucker