Rambus Inc.

Inapac Technology, Inc.

Kabushiki Kaisha Toshiba

Douglas W Gorgen

Adrian E Ong

Shoichi Shimizu

Jerome D Harr

Karl R Hense

Robert W Donner

Systems and methods for synchronizing communication between devices include using a test circuit to measure a propagation time through a delay circuit. The propagation time is used to determine an initial delay value within a delay lock loop. This delay value is then changed until a preferred delay value, resulting in synchronization, is found. In various embodiments, used of the initial delay value increases the speed, reliability or other beneficial features of the synchronization.

Delay lock loop delay adjusting method and apparatus

A circuit and a method for determining the operating point of a semiconductor device are provided. An operating point circuit is implemented on a semiconductor device and includes a delay element that receives a first signal and produces a second signal. Since the delay changes depending on the process variation of the semiconductor device, the current temperature of the semiconductor device, and the current supply voltage supplied to the semiconductor, the delay between the first signal and the second signal can be used to determine the operating point of the semiconductor device.

Circuit and method for determining the operating point of a semiconductor device

Switched pull down (SPD) ECL circuits have a switching circuit within the pull down portion of the output stage, so that a large portion of the total pull down current is switched to the negative going output node, and so that a small portion of the total pull down current is switched to the positive going output node. The negative going output node has a larger that normal ECL pull down current attached to it. The larger pull down current on the negative going node discharges the output capacitor in a shorter period of time. The shorter discharge time of negative going output results in a shorter fall delay time. Two smaller current sources are connected to each of the two differential ECL outputs to insure that both pull up transistors are forward biased so as to provide an adequate noise margin and insure correct circuit operation. Forward biasing the pull up transistors with a minimum acceptable amount of bias current at the emitters of the output pull up transistors provides proper immunity to noise.

Switched pull down emitter coupled logic circuits

Growing community of inventors

San Jose, CA, United States of America

Douglas W Gorgen