Sun Microsystems, Inc.

Douglas W Forehand

Gary S Goldman

Deviprasad Malladi

Larry D Smith

Raymond E Anderson

Tanmoy Roy

Karl A Sauter

Christopher Chen

Thomas J Pelc

Ray Lamoreaux

In accordance with the present invention, a cache memory subsystem includes a processor, a cache control unit and a SRAM serving as the cache memory. The SRAM is a synchronous SRAM. The cache control unit provides appropriately timed control signals to the SRAM when the processor is accessing the cache memory. The SRAM can be either a pipelined architecture SRAM (register output SRAM) or a flow-through access architecture SRAM (latch output SRAM). The cache control unit is selectably configured to operate in a pipelined mode (1-1-1) or a flow-through (2-2) mode. The cache control unit is configured in the 1-1-1 mode when the SRAM is a pipelined architecture SRAM having a clock rate equal to the processor. When the SRAM is a flow-through architecture SRAM that cannot be clocked at the same rate as the processor, the cache control unit is configured in the 2-2 mode and the SRAM is clocked at a clock rate half of the processor clock rate.

Multiple-mode external cache subsystem

A system and method for measuring the equivalent series resistance (ESR) of one or more capacitors using an impedance analyzer, whereby the capacitors are joined to the impedance analyzer with a conductive adhesive. The conductive adhesive may advantageously provide for an electrically and mechanically stable connection between the capacitor and the remainder of the electrical circuit used to measure the ESR of the capacitor. The conductive adhesive may include heat activated or cold solder, or conductive putty. The system comprises a measuring unit for sweeping a frequency range to find the minimum impedance for the capacitor and a connector assembly for holding the capacitor in an electrically and mechanically stable connection using the conductive adhesive. The connector assembly includes a mating portion adapted for electrically connecting the connector assembly to an I/O port of the measuring unit and a terminal portion that accommodates a connection to the capacitor using the conductive adhesive. The method comprises connecting a mating portion of the connector assembly to the impedance analyzer. Next, the impedance analyzer is calibrated, and the capacitor is then connected to a terminal portion of the connector assembly using the conductive adhesive. Finally, the impedance analyzer sweeps a frequency range to find the ESR for the capacitor. The method may also measure the ESR of each of a number of capacitors using an impedance analyzer. The method may connect in series the number of capacitors to the connector assembly using the conductive adhesive. The method determines the equivalent series resistance of each of the number of capacitors by dividing the minimum impedance by the number of capacitors. The method may also comprise selecting one or more capacitors, measuring the ESR of each of the capacitors, and determining a desired number of each of the capacitors for placing into a power distribution system.

Method and system for measuring equivalent series resistance of capacitors and method for decoupling power distribution systems

A method and structure for routing electrically conductive interconnect paths through a printed circuit board. The printed circuit board includes a plurality of insulating layers and conductive layers, including at least one electrically conductive voltage supply layer for receiving a first supply voltage. A plurality of voltage supply pad patterns are located at the upper surface of the printed circuit board. Each voltage supply pad pattern includes two or more electrically conductive pads which are coupled by one or more electrically conductive traces. Electrically conductive via plugs extend through the printed circuit board to connect the voltage supply layer to the voltage supply pad patterns. Each via plug is connected to one corresponding voltage supply pad pattern, thereby allowing each via plug to provide the first supply voltage to a plurality of pads at the upper surface of the printed circuit board. As a result, the number of via plugs required for routing the first supply voltage through the printed circuit board is reduced, thereby increasing the layout area available for routing conductive traces in other layers of the printed circuit board.

Optimized routing scheme for an integrated circuit/printed circuit board

A structure and method for controlling the junction temperature of a semiconductor chip in an electronic system. A temperature sensing device and the chip whose junction temperature is to be monitored are located adjacent to one another on the same interconnect structure. A thermally conductive lid can also be attached to the interconnect structure, thereby enclosing the temperature sensing device and the chip within in a closed cavity. Dedicated pins extend from the temperature sensing device through the interconnect structure, for connection to a temperature control circuit. By locating the temperature sensing device on the same interconnect structure as the chip, and within a common enclosure, the temperature sensed by the temperature sensing device is an accurate representation of the actual junction temperature of the chip. By obtaining an improved reading of the actual junction temperature, the operation of the temperature control circuit can be optimized.

Integrated junction temperature sensor/package design and method of

A method of locating a socket on a printed circuit board which includes the steps of fabricating a plurality of pads and one or more fiducials on the upper surface of the printed circuit board, optically aligning a drill with the fiducial, and then drilling a socket hole through the printed circuit board at the location defined by the fiducial. A peg of the socket is inserted into the socket hole to align the socket with the printed circuit board. Alternatively, a method for locating holes on a printed circuit board includes the steps of forming a master tooling hole through the printed circuit board, locating a fiducial on the printed circuit board using the master tooling hole as a guide, focusing on the fiducial with an optically alignable drill, thereby aligning the drill, and then drilling a hole through the printed circuit board using the aligned drill. The fiducial is selected to be a material which provides a sharp optical contrast with the area surrounding the fiducial, thereby allowing the drill to be easily and accurately focused on the fiducial.

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Mountain View, CA, United States of America

Douglas W Forehand