Hewlett-packard Development Company, L.P.

Hewlett-packard Company

Adv Antest Corporation

Douglas Vincent Larson

Paul David Gootherts

Blaine Douglas Gaither

Rochit Rajsuman

Anthony Le

Benjamin Daniel Osecky

Harshadrai Parekh

Swapneel Kekre

Richard Glen Fowles

Marcia E McConnell

Robert Johnson

Colin Edward Honess

Carol Qiao Tong

An embodiment of the invention provides an apparatus and method for controlling access by a read-write spinlock with no mutual exclusion among readers. The apparatus and method perform the steps of using values in a data structure in the read-write spinlock to control read access to a shared object and using values in the data structure and a guard lock to control write access to the shared object.

Read-write spinlock

Systems, methods, and devices, including computer executable instructions for transferring threads are described. The method comprises determining an idle processor by checking a handoff state of the processor prior to placing an identified runnable thread in a run queue of an idle processor. The method also comprises transferring the runnable thread to a determined idle processor by setting the handoff state of the processor to a handle of the runnable thread.

Thread hand off

A processor of an apparatus in an example upon a failure of an earlier attempt to directly acquire ownership of an access coordinator for a resource shared with one or more additional processors, locally determines an amount to delay a later attempt to directly acquire ownership of the access coordinator. Upon a failure of the later and/or a subsequent attempt to directly acquire ownership of the access coordinator the processor would enter into an indirect waiting arrangement for ownership of the access coordinator.

Processor acquisition of ownership of access coordinator for shared resource

In an embodiment of the invention, a method for a memory-mapped lazy preemption control, the method includes: incrementing a counter value if an operating system attempts to involuntarily context switch out a thread and fails to context switch out the thread because the thread has a flag set; checking a counter value to determine a degree of abusiveness of a thread; and based upon the degree of abusiveness, determining if a voluntary contact switch out should be performed or should not be performed on the thread.

System for controlling context switch of deferred requests using counter and flag setting of thread accessing shared resource or entering code region

Systems, methods, and devices are provided for time measurement. One embodiment includes a method for measuring time on multiprocessor systems. The method includes allocating a memory space to a thread to be used to communicate with an operating system and saving a context switch count, an offset, and a scale factor, received from the operating system, in the memory space.

Time measurement using a context switch count, an offset, and a scale factor, received from the operating system

A method of and computer system for selecting a processor of a computer system on which to launch a processing thread is described. Each processor load is compared with a volunteer load of a volunteer information. If the processor load is lower than the volunteer load, the volunteer information is updated with the compared processor information. If the compared processor is the current volunteer and the compared processor load is higher than the volunteer load, the volunteer information is updated with the compared processor information.

Processing thread launching using volunteer information

In an embodiment of the invention, a method for lazy signal blocking, includes: when a program is going to enter a critical region of code where signals will be blocked, then setting an enabled flag and marking a signal mask with signals to be blocked, wherein the enabled flag and the signal mask are in a memory address space of the program; and when the program has left the critical region of code where signals will be blocked, then clearing the enabled flag.

Memory mapped lazy signal blocking

A method of allocating memory operates to avoid overlapping hot spots in cache that can ordinarily cause cache thrashing. This method includes steps of determining a spacer size, reserving a spacer block of memory from a memory pool, and allocating memory at a location following the spacer block. In an alternative embodiment, the spacer size is determined randomly in a range of allowable spacer size. In other alternative embodiments, spacers are allocated based upon size of a previously allocated memory block.

Method and program product for avoiding cache congestion by offsetting addresses while allocating memory

An ATE calibration method and system that does not require external test equipment to calibrate individual functional pins and provides balanced timing skews among the functional pins and pincards is disclosed. A functional pin in the test system is selected as a reference or &ldquo;golden&rdquo; pin and another is selected as a precision measurement unit (PMU). External test equipment and the reference PMU are used to measure the AC and DC characteristics of the reference pin, and any deviation represents a measurement error in the reference PMU. All functional pins in the test system can be measured against the reference pin using the reference PMU, taking into account the measurement error, without the need for external test equipment. To ensure that skews are balanced among all pins, the location of the reference pin is selected to be as close as possible to the midpoint of the functional pin range.

Calibration method for system performance validation of automatic test equipment

Branch predictions are adjusted by interrupting a central processing unit and observing a pending branch instruction. An interrupt is generated using a counter, timer, or software-based interrupt. The interrupt causes a prediction adjustment routine to execute, which in turn determines whether a pending branch instruction will branch. The actual branch behavior of the branch instruction is compared to the predicted branch behavior of the branch instruction, and the prediction is adjusted accordingly based on the accuracy of the prediction and previous branch behavior. After the prediction has been adjusted (if necessary), execution returns to the program that contains the branch instruction that was evaluated.

Growing community of inventors

Santa Clara, CA, United States of America

Douglas Vincent Larson