Texas Instruments Corporation

Lsi Logic Corporation

North Carolina State University

Douglas Ticknor Grider

Rajesh B Khamankar

Haowen Bu

Xiang-Zheng Bo

Hiroaki Niimi

Brian Keith Kirkpatrick

Mehmet C Ozturk

James Joseph Chambers

Jimmie J Wortman

Katherine E Violette

Xiangzheng Bo

P R Chidambaram

Sheldon Aronowitz

Amitabh Jain

Gobi R Padmanabhan

Ping Jiang

Alwin J Tsao

Srinivasan Chakravarthi

Sunil V Hattangady

Pr Chidambaram

James O Kimball

Toan Tran

David Gerald Farber

John Howard MacPeak

Stanton Petree Ashburn

Patrick Robert Smith

Donald S Miles

Jon S Owyang

April Gurba

Yu-Lam Ho

Chi-Yi Kao

Mahesh K Sanganeria

Terence Breedijk

Stanton P Ashburn

Mark Stephen Rodder

Mahalingam Nandakumar

Freidoon Mehrad

Rick L Wise

Lindsey H Hall

Robert Kraft

Thomas C Holloway

F Scott Johnson

Periannan Chidambaram

George R Misium

Stephen A Keller

Brian Edward Hornung

Zhihao Chen

Brian Ashley Smith

Byron Joseph Palla

Vincent Maurice McNeil

Paul Edward Nicollian

Bo-Yang Lin

Steve Hsia

Michelle N Nguyen

John H Macpeak

Chidi P R Chidambaram

Che Jen Hu

A method of forming an integrated circuit relative to a wafer comprising a semiconductor substrate. The method first forms a first dielectric layer having a first thickness and along the substrate, the first forming step comprising plasma etching the wafer in a first substrate area and a second substrate area and thereafter growing the first dielectric layer in the first substrate area and the second substrate area. After the first step, the method second forms a second dielectric layer having a second thickness and along the substrate in the second substrate area, the second thickness less than the first thickness, the second forming step comprising removal of the first dielectric layer in the second substrate area without plasma and until a surface of the substrate is exposed and growing the second dielectric layer in at least a portion of the surface.

Split gate memory cell fabrication and system

A method of forming an integrated circuit includes forming a first layer having a first material type over a first side of a semiconductor wafer. A second layer having a second different material type is removed from a second opposing side of the semiconductor wafer using a first process that removes the second material type at a greater rate than the first material type. Subsequent to removing the second layer, the first layer is removed using a second different process.

Method for stripping one or more layers from a semiconductor wafer

In accordance with some examples, a system comprises a substrate layer having an outer surface. The system also comprises a plurality of trenches extending from the outer surface into the substrate layer. The system then comprises a plurality of active regions with each active region positioned between a different pair of consecutive trenches of the plurality of trenches. The system also comprises a dielectric layer disposed in each of the plurality of trenches and on each of the plurality of active regions. The system then comprises a gate layer disposed on the dielectric layer and extending at least partially into each of the plurality of trenches.

Partially disposed gate layer into the trenches

In some examples, an integrated circuit comprises a first plate, a second plate, and a dielectric layer disposed between the first and second plates, the first and second plates and the dielectric layer forming a vertical capacitor, wherein the first and second plates and the dielectric layer of the vertical capacitor are disposed on an isolation region of the integrated circuit.

Integrated circuit including vertical capacitors

In some examples, a transistor includes a first well doped with a first-type dopant having a first concentration. The transistor also includes a gate oxide layer on a portion of the first well and a gate layer on the gate oxide layer. The transistor further includes a first segment of a second well doped with the first-type dopant having a second concentration, the first segment underlapping a first portion of the gate layer. The transistor also includes a source region doped with a second-type dopant having a third concentration, the source region in the first segment. The transistor further includes a drain region doped with the second-type dopant having a concentration that is substantially the same as the third concentration.

Transistors with dual wells

In accordance with some examples, a system comprises a substrate layer having an outer surface. The system also comprises a plurality of trenches extending from the outer surface into the substrate layer. The system then comprises a plurality of active regions with each active region positioned between a different pair of consecutive trenches of the plurality of trenches. The system also comprises a dielectric layer disposed in each of the plurality of trenches and on each of the plurality of active regions. The system then comprises a floating gate layer disposed on the dielectric layer and extending at least partially into each of the plurality of trenches.

A method of manufacturing a semiconductor includes applying a planarization material to a substrate and forming an opening in the planarization material. The opening is filled with polysilicon. A plurality of etching modulation sequences are applied to the substrate, each of the etching modulation sequences including: applying a first etching process to the substrate, wherein the first etching process is more selective to polysilicon than the planarization material; and applying a second etching process to the substrate, wherein the second etching process is more selective to the planarization material than the polysilicon.

Method of fabricating semiconductors

A split-gate flash memory cell (cell) includes a semiconductor surface. A first control gate (CG) on a first floating gate (FG) and a second CG on a second floating gate (FG) are on the semiconductor surface. A common source or common drain is between the first and second FG. A first select gate and a second select gate on a select gate dielectric layer is between a first BL source or drain (S/D) and the first FG and between a second BL S/D and the second FG, respectively. The first select gate has a first pocket region that has a first doping distribution different from a second doping distribution in a second pocket region associated with the second select gate which reduces a variation in read current (Ir) for the cell between measuring Ir using the first select gate and measuring Ir using the second select gate.

Feed-forward bidirectional implanted split-gate flash memory cell

An integrated circuit containing an analog MOS transistor may be formed by implanting drain extensions with exactly four sub-implants wherein at least one sub-implant implants dopants in a substrate of the integrated circuit at a source/drain gate edge of the analog MOS transistor at a twist angle having a magnitude of 5 degrees to 40 degrees with respect to the source/drain gate edge of the analog MOS transistor, for each source/drain gate edge of the analog MOS transistor, wherein a zero twist angle sub-implant is perpendicular to the source/drain gate edge. No more than two sub-implants put the dopants in the substrate at any source/drain gate edge of the analog MOS transistor. All four sub-implants are performed at a same tilt angle. No halo implants are performed on the analog MOS transistor.

High tilt angle plus twist drain extension implant for CHC lifetime improvement

An integrated circuit capacitor. The capacitor includes a substrate, a first conductor, and a first insulating region between the first conductor and the substrate. The capacitor also includes a second conductor, a second insulating region between the first conductor and the second conductor, a third conductor, and a third insulating region between the first conductor and the third conductor. The capacitor also includes a fourth conductor and a fourth insulating region between the first conductor and the fourth conductor.

Three dimensional three semiconductor high-voltage capacitors

A silicon nitrate layer () is formed over a transistor gate () and source and drain regions (). The as-formed silicon nitride layer () comprises a first tensile stress and a high hydrogen concentration. The as-formed silicon nitride layer () is thermally annealed converting the first tensile stress into a second tensile stress that is larger than the first tensile stress. Following the thermal anneal, the hydrogen concentration in the silicon nitride layer () is greater than 12 atomic percent.

High performance CMOS transistors using PMD liner stress

Growing community of inventors

McKinney, TX, United States of America

Douglas Ticknor Grider