Cypress Semiconductor Corporation

Qualcomm Incorporated

Micro Linear Corporation

Resonext Communications, Inc.

National Semiconductor Corporation

Rf Micro Devices, Inc.

Nanoamp Solutions, Inc.

Irf Semiconductor, Inc.

Douglas Sudjian

David H Shen

Ali Rezvani

A detection circuit that can accurately detect signal peak is described. In an exemplary design, the detection circuit includes a bias voltage generator and a MOS transistor. The bias voltage generator provides a bias voltage as a function of temperature. The MOS transistor receives an input RF signal and the bias voltage and provides a rectified signal, which may be a linear function of the input RF signal and may have reduced deviation with temperature due to the bias voltage. The bias voltage generator may generate the bias voltage based on a temperature-dependent current having a slope selected to reduce deviation in the rectified signal with temperature. An offset canceller may cancel a reference voltage from the rectified signal and provide an output signal. A bulk bias generator may generate a bulk voltage for the bulk of the MOS transistor as a function of temperature to improve operating speed at higher temperature.

Detection circuit for overdrive conditions in a wireless device

Techniques for providing a comparator incorporating amplitude hysteresis. In an exemplary embodiment, a current offset stage is coupled to a comparator having a folded cascode architecture. The current offset stage offsets the current generated from an input stage to delay switching of the comparator output to implement amplitude hysteresis. In an exemplary embodiment, rail-to-rail input voltages may be accommodated by providing dual NMOS and PMOS input stages. In another exemplary embodiment, the amplitude hysteresis may be controlled by an adjustable threshold voltage. In yet another exemplary embodiment, a constant transconductance gbias circuit may be provided to maintain the stability of the threshold voltage across input common-mode voltage and/or other variations.

Comparator with hysteresis

A high-speed latch is disclosed that can function at high-speed input clocking frequencies. The active loads used within the latch design exhibit an input impedance that is inductive to the rest of the circuit to improve the driving capability of the overall latch in the presence of loading capacitances. The latch circuit, when used in a system or stand alone divider, will consume very low power while reducing the silicon die area. Possible applications include but are not limited to frequency dividing and counting applications. Of particular interest is the use of this high-speed latch in a prescaler divider as a part of a charge pump phase-locked loop design for single chip CMOS multi-band and multi-standard radio frequency transceiver integrated circuits.

Low power high speed latch for a prescaler divider

An improved clock recovery system, phase-locked loop, and phase detector are provided as well as a method for generating charge pump signals. The clock recovery system includes a phase-locked loop. The phase-locked loop includes a phase detector and a voltage-controlled oscillator. The phase detector generates pump signals that change linearly with respect to differences between phases of an incoming signal and a clocking signal. The oscillator is coupled to receive the pump signals and produce a clocking signal at a frequency not exceeding the frequency of the incoming signal. For example, the oscillator can produce clocking signals at one-half the frequency of the incoming signal, where the incoming signal is preferably a maximum bit rate of a data signal from which the clock signal is recovered. The phase detector can include a first flip-flop and second flip-flop. The first flip-flop receives the incoming signal and a differential first pair of clocking signals, whereas the second flip-flop is coupled to receive a delayed incoming signal and a differential second pair of clocking signals. The differential second pair of clocking signals are delayed 90&#xb0; from the first pair of clocking signals to present a phase detector that samples using a quadrature clocking signal generated from the oscillator.

System and method for recovering a clock using a reduced rate linear phase detector and voltage controlled oscillator

A charge pump is disclosed which generates higher and more symmetric source and sink currents that prior designs and reduces the multiple frequency sidebands that occur in a voltage controlled oscillator of a phase-loop synthesizer. Other improvements are the reduction in reference frequency feed-through, charge sharing and noise transient coupling and phase noise in the phase-locked loop. Possible applications include but are not limited to charge pump phase-locked designs for single chip CMOS multi-band and multi-standard radio frequency integrated circuits.

Symmetric charge pump

An improved clock generation circuit using a multi-phase phase-locked loop (PLL) circuit design that incorporates a dual set of PLLs. A first PLL maintains frequency lock control of an oscillator while a second PLL controls various phase outputs from delay circuits external to the oscillator which are locked in time delay with phase outputs from the oscillator. In this fashion, 2N phase outputs can be achieved with an oscillator that only produces N phase outputs. Furthermore, the second PLL uses a three-input phase detector that compares the phase output from one of the delay circuits external to the oscillator with a pair of phase outputs from the oscillator. Depending on the timing relationship of those output phases, the three-input phase detector will yield either a predominant pump-up pulse or a predominant pump-down pulse, through which the second PLL will use these signals to control the phase output of the external delay circuits relative to the phase outputs from the oscillator.

Triple input phase detector and methodology for setting delay between two sets of phase outputs

Techniques to improve the operating speed and switching performance of a latch having an integrated gate. In one design, the latch includes first and second differential amplifiers and a feedback circuit (e.g., a third differential amplifier). The first differential amplifier has a number of non-inverting inputs (e.g., configured to implement an OR function) and an inverting input, receives and senses input signals applied to the non-inverting inputs during a &ldquo;sensing&rdquo; phase, and provides a differential output. The second differential amplifier latches the output during a &ldquo;latching&rdquo; phase. The feedback circuit detects the non-inverting output and provides a control signal for the inverting input of the first differential amplifier. The feedback circuit can provide positive feedback, and can dynamically adjust the inverting input to provide improved switching performance. A fourth differential amplifier receives a differential clock signal, and activates the first and second differential amplifiers during the sensing and latching phases, respectively.

High-speed latch with integrated gate

An improved clock generation circuit that utilizes a multi-phase PLL architecture is provided as well as a method for generating multiple phase outputs. The clock generation circuit can produce multiple phase outputs with the oscillator only producing approximately one-half of those multiple phase outputs. The other half of the phase outputs come from a set of delay circuits external to the oscillator. In this fashion, the oscillator can operate at relatively high frequencies yet not suffer the consequences of trying to decrease the tap-to-tap delay using additional series delay elements if numerous phase outputs are needed. Instead, one-half of the taps are provided external to the oscillator. Thus, the phase outputs from the oscillator are interleaved with phase outputs from an external set of delay circuits, where the oscillator is under frequency lock control using a first PLL and the external delay circuits maintain the frequency lock of the oscillator, yet are delayed in phase by virtue of a phase lock control of a second PLL. The combination of dual PLLs ensures consistent phase alignment between the oscillator phase outputs and the external delay circuit phase outputs. Phase control is ensured through the second PLL and, importantly, regularly spaced phase outputs produced in an interleaved fashion can be achieved for high density phase outputs exceeding, for example, 8, 16, or even 32 multiple phase outputs from the PLL circuit.

System and method for generating interleaved multi-phase outputs from a nested pair of phase locked loops

Techniques to isolate noise-sensitive circuits from noise generated by nearby circuits. In one design, a quiet region is formed on a die when surrounded by a deep n-well formed on top of a p-type substrate. The deep n-well is heavily doped n-type and forms a depletion region at the junction with the p-type substrate. The depth and width of the depletion region is dependent on the doping concentration of the deep n-well and the amount of reverse bias voltage applied to the deep n-well. In general, a wider and deeper depletion region may be formed by more heavily doping the deep n-well and applying a higher reverse bias voltage. By properly constructing the deep n-well and applying a high reverse bias voltage, a deep and wide depletion region may be formed to provide a barrier against noise from entering the quiet region.

Method and apparatus for isolating circuits using deep substrate n-well

A logic gate that includes a first differential amplifier and a feedback circuit. The first differential amplifier has a number of first (e.g., non-inverting) inputs and a second (e.g., inverting) input, receives and senses input signals applied to the non-inverting inputs, and provides a differential output that is a particular logic function (e.g., an 'OR') of the input signals. The non-inverting inputs may correspond to the gates of a number of transistors coupled in parallel to form an OR function. The feedback circuit detects the (e.g., non-inverting node of the) differential output and provides a control signal for the inverting input of the first differential amplifier. The logic gate typically further includes a second differential amplifier that senses and further drives the differential output.

High-speed logic gate

A delay cell for use within a voltage controlled oscillator capable of operating at two different selectable frequencies, the delay cell having a first delay stage including a first differential pair of transistors, wherein the emitter or each transistor is coupled to a first common node and further wherein a first current exiting the first common node is selectively variable. The delay cell further having a second delay stage including a second differential pair of transistors, each having an emitter coupled to a second common node wherein a second current exiting the second common node is selectively variable and wherein a sum of the first current and the second current is substantially constant. The amount of delay associated with the first delay stage is dependent upon the level of the first current. The delay cell provides for a more linear relationship between output frequency and input voltage by controlling the first current through the first delay stage and the second current through the second delay stage such that a decrease in the first current is accompanied by an increase in the second current and, conversely, an increase in the first current is accompanied by a decrease in the second current and the sum of the first current and second current is substantially constant.

Voltage controlled ring oscillator delay

The present invention is a CML to CMOS converter which includes a bipolar input stage, a current source/current sink stage, and an output stage. The converter is able to transfer a CML input voltage differential to a CMOS compatible voltage having constant high and low voltage levels with a constant duty cycle. The bipolar input stage receives an incoming CML voltage differential and steps the voltage levels down. Utilizing the stepped down CML voltage differential, the current/source sink drives the output stage by maintaining an equal current source and current sink to and from the output stage, ensuring that an output voltage at the output stage rises and falls to constant high and low voltage levels, thereby maintaining a constant duty cycle. A first pair of NMOS transistors, coupled to the output stage drive current to the output stage from a high input voltage rail whenever the input differential is high. A first pair of PMOS transistors, coupled to the output stage sink current from the output stage to a low input voltage rail whenever the input voltage is low. The transistors are arranged and biased in order to ensure that the current sink transistors are not on as current is sourced to the output stage from the high input voltage, and the current source transistors are not on as current is sunk from the output stage to the low input voltage.

High performance CML to CMOS converter

A control signal generation circuit is particularly suited for use in a phase lock loop circuit. The control signal generation circuit provides a control signal to a voltage controlled oscillator. The control signal is provided in response to a phase difference signal provided by phase comparator circuitry. Charge pump circuitry includes a primary current source that provides a primary current signal in response to the phase/frequency difference signal. A secondary current source provides a secondary current signal, also in response to the phase/frequency difference signal. The control signal generation circuit also includes filter circuitry. The filter circuitry includes a resistance element connected between a first input, which is connected to receive the primary current signal, and a second input, which is connected to receive the secondary current signal. A capacitance element, connected in series to the resistive element, is connected between the second input and ground. A voltage, relative to ground, is developed at the first input and is provided as the control signal.

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Santa Clara, CA, United States of America

Douglas Sudjian