Hewlett-Packard Development Company, L.p.

Douglas Shelborn Stirrett

Reid James Riedlinger

Ted Scott Rakel

Gregg Bernard Lesartr

James Kwok-Yue Wai

Steven Ray Afleck

Benjamin Joseph Haass

One disclosed embodiment may comprise a design method for a dynamic circuit system. The method may include providing a design for a single stage network comprising a pull-down network that is configured to perform a desired logic function according to a plurality of inputs. The method may also include designing a multi-stage network that includes at least two stages, each of the at least two stages including a pull-down network that receives a respective portion of the plurality of inputs and each of the at least two stages cooperating to perform the desired logic function.

Circuit and circuit design method

A processor purging system comprising a translation lookaside buffer (TLB) having a plurality of translation pairs, at least one memory cache, and logic configured to detect whether at least one of the translation pairs corresponds to a purge signal. The logic is further configured to assert a purge detection signal indicative of whether at least one translation pair corresponds to the purge signal and to determine, based upon the purge detection signal, whether to search the memory cache for a translation pair corresponding to the purge signal.

Processor purging system and method

A device testing system that has automated test equipment (ATE), which interfaces to a device under test (DUT). The device testing system selects a test set of data including a plurality of test pairs, indicative of DUT parameter values. The system, selects a subset of the plurality of test pairs from the test set of data tests the DUT via the ATE with a portion of the selected subset based upon the test results of at least one of the test pairs.

System and method for testing devices

DC margin of a latch of a circuit under design is determined by performing three simulations. A simulation is performed to find the trip voltage of the forwarding inverter of the latch. A second simulation is performed to find the one margin of the latch. Lastly, a third simulation is performed to find the zero margin of the latch. During each of the simulations to find the one margin and the zero margin, the worst case input signal path from the various driver circuit elements and signal paths within the circuit under design is determined analytically by accumulating weighted resistance of each of the circuit elements along the signal paths. The weights assigned to the circuit elements are empirically determined based on the topology configuration of each of the circuit elements, e.g., the type circuit element, the signal being passed through the circuit element and whether a threshold voltage drop occurs between the drive circuit element and the pass circuit element.

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Fort Collins, CO, United States of America

Douglas Shelborn Stirrett