Analog Devices,inc.

Precision Monolithics, Inc.

Elantec, Inc.

Douglas S Smith

Derek F Bowers

James R Butler

Edward C Bee

An active folded cascode includes an amplifier transistor and a source follower transistor configured as a folded cascode with the drain of the amplifier transistor and the source of the follower transistor connected to form a gain node. A feedback transistor has its gate and drain connected to the source and gate of the follower transistor while bias current provided to the drain of the feedback transistor by a current source maintains the gain node at a fixed voltage with respect to a reference voltage. Coupling of the voltage at the gain node to the gate of the source follower transistor by the feedback transistor reduces the effective source impedance of the source follower transistor, providing improved gain and bandwidth properties for the active folded cascode circuit.

Active folded cascode

A wide dynamic range transconductance stage has two branches, each branch being composed of a plurality of transconductance circuit paths. Each circuit path has a greater transconductance than the other circuit paths for its branch within a respective sub-range of the input signal range for the stage as a whole, with each path dominating the other paths for its branch within its respective sub-range. The overall bandwidth for the stage, its g.sub.m, its noise characteristics and its input voltage range are enhanced as a result. Bandwidth and slew rate may be independently optimized by the designer. Two paths are used for each branch in the preferred embodiment, with one path consisting of a bipolar transistor and the other path either a field effect transistor or a resistor degenerated bipolar transistor. Multiple paths may be used based on the same principle.

Wide dynamic range transconductance stage

A first Schottky diode is connected between the source of a first enhancement JFET and a low voltage line. The drain of the first enhancement JFET is connected through a first active load current source to a high voltage line, and also through a second Schottky diode and a second active load current source to the low voltage line. The first Schottky diode produces a voltage drop which maintains the source of the first enhancement JFET positive with respect to the low voltage line. The second Schottky diode produces a voltage drop complementary to that of the first Schottky diode, which causes the circuit to produce an output voltage across the second current source having a logically low level close to that of the low voltage line. This low output voltage positively turns off a first enhancement JFET of a next stage even at elevated temperatures where the voltage threshold is close to zero, since the source of the first enhancement JFET is held positive at one diode drop above the low voltage line by the first Schottky diode. A second enhancement JFET may be connected to supply current which maintains the first Schottky diode conductive at all times, and also to provide positive feedback to the first enhancement JFET by source coupling through the resistance of the first Schottky diode which enhances switching.

Wide temperature range MESFET logic circuit

An analog switching circuit may be implemented with MESFETs without forward biasing the switching device, and is applicable to JFET switches in general. Switching currents are provided from a nominal input line which closely tracks the true analog input voltage, but is segregated therefrom. A current supply fed from the nominal input line provides transient charging current to the gate of the switching transistor during the switching transition from OFF to ON states. Voltage setting devices hold the gate and source of the enhancement-mode current supply at approximately the nominal supply voltage level when the switching transistor is ON, while a control section holds the gate and source of the current supply device at a negative reference voltage level when the switching transistor is OFF. In either case, the current supply device is inhibited from delivering gate current to the switching transistor during steady state operation.

JFET analog switch with gate current control

An analog switching circuit may be implemented with MESFETs without forward biasing the switching device, and is applicable to JFET switches in general. Switching currents are provided from the nominal input line which closely tracks the true analog input voltage, but is segregated therefrom. A current supply fed from the nominal input line provides transient charging current to the gate of the switching transistor during the switching transition from OFF to ON states. Voltage setting devices hold the gate and source of the enhancement-mode current supply at approximately the nominal supply voltage level when the switching transistor is ON, while a control section holds the gate and source of the current supply device at a negative reference voltage level when the switching transistor is OFF. In either case, the current supply device is inhibited from delivering gate current to the switching transistor during steady state operation.

A voltage reference circuit is described which is capable of providing either an internally generated voltage having a trimming capability, or an externally generated voltage, with the use of only two pins. The internal voltage is connected through an interrupt circuit to an input/output terminal, which can also receive an externally generated voltage. A trimming terminal is used to apply trimming voltage signals to adjust the internally generated voltage. To convert from the internal to the external voltage source, an interrupt voltage is applied to the trimming terminal which is outside of the normal trimming voltage range. This interrupt voltage actuates an interrupt circuit to interrupt the connection between the internal voltage source and input/output terminal, leaving the output terminal available for the external voltage source.

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Sunnyvale, CA, United States of America

Douglas S Smith