Silicon Laboratories Inc.

Silicon Labs Cp, Inc.

Cirrus Logic Inc.

Cygnal Integrated Products, Inc.

Witricity Corporation

Crystal Semiconductor Corporation

Other

Harris Corporation

Cyngal Integrated Products, Inc.

Douglas S Piasecki

Ka Yin Leung

Eric J Swanson

Douglas R Holberg

Kenneth Wilson Fernald

Wai Laing Lee

Donald E Alfano

Karl Ernesto Thompson

Paul Highley

Danny Joe Allred

Brian Caloway

Carlos Esteban Mu&ntilde;oz

Alvin C Storvik, Ii

Thomas Saroshan David

Alvin Chuck Storvik

Jia-Hau Liu

Michael Keith Odland

Timothy Thomas Rueger

Stefan N Mastovich

Golam Rasul Chowdhury

Alan Storvik

Donald A Kerth

Alan Lee Westwick

Zhong You

Marty Lynn Pflum

Michael L Duffy

Russell A Hershbarger

William Hong

James Dub Austin

Bruce Del Signore

Kevin Kwak

Alvin C Storvik Ii

Carlos Estaban Mu&ntilde;oz

A current shunt monitor (CSM) circuit for monitoring the current through a sense resistor. An analog circuit provides an analog output signal proportional to the voltage across the sense resistor. A power supply includes a fixed voltage power supply at a first voltage supply level and a floating power supply. The floating power supply operates at a second voltage supply level referenced from the voltage level on a voltage input and a floating ground. The voltage input varies from a voltage level above the first voltage supply level to a voltage level below the first voltage supply level, and the floating power supply provides power to the analog circuit at least when the voltage level of the voltage input is above the first voltage supply level. A crossover circuit switches power from the floating power to the fixed voltage power supply at the first voltage supply level upon detecting the voltage level on the voltage input proximate in value to the first voltage supply level.

Current shunt monitor

A configurable transmit/receive multiplexed coil monitoring (CMCM) device is provided having a plurality of dual function I/O connections connectable to a plurality of coils. The CMCM device is configurable to selectively drive AC transmit signals to any of the plurality of dual function I/O connections, while simultaneously monitoring voltage and phase information received as AC voltages at the dual function I/O connections in a multiplexed manner. The CMCM device is further configured such that while a selected I/O connection is selected to receive voltage and phase information from a particular I/O connection, no AC transmit signal can be driven to that selected particular I/O connection. Embodiments may include a multiplexer and one or more receive circuits configured to receive and digitalize received AC signals for processing by a digital signal processor. Embodiments may also include selectable Class-D drivers connected to the plurality of I/O connection, wherein each Class-D driver may be configured to receive pulse width modulation (PWM) signals from a PWM circuit for amplification and output as an AC transmit signal.

Configurable wireless charging transmit and receive monitoring device

An LCD controller includes a charge pump for generating a charge voltage responsive to an external voltage and a clock signal. The controller further includes an oscillator for generating the clock signal responsive to an oscillator control signal. An LCD driver voltage circuit generates a plurality of LCD driver voltages for driving segments of an associated LCD display. A loop control circuit within the LCD controller monitors an LCD driver voltage from the LCD driver voltage circuit and generates the oscillator control signal responsive thereto to enable and disable the oscillator.

System and method for LCD loop control

An LCD controller includes a charge pump circuit for generating a charge voltage responsive to an external voltage and a clock signal. An oscillator generates the clock signal responsive to at least one bias voltage. The oscillator has a high power mode of operation and a low power mode of operation. Bias circuitry for applies the at least one bias voltage to the oscillator. The at least one bias voltage is applied to the oscillator from an external source in the high power mode of operation and the at least one bias voltage is applied to the oscillator from a source within the oscillator in the low power mode of operation. An LCD driver voltage circuit generates a plurality of LCD driver voltages for driving segments of an LCD display responsive to the charge voltage.

LCD controller with oscillator prebias control

In one embodiment, a data acquisition circuit includes an analog multiplexer to receive analog signals and select an analog signal for output, an ADC coupled to the multiplexer to receive the analog signal and perform a conversion of the analog signal to a N-bit digital value in at least N clock cycles, and a controller coupled to the ADC to enable the ADC to compare the analog signal to a second analog signal in a single clock cycle.

Performing digital windowing in an analog-to-digital converter (ADC)

A metering system can include a pull up circuit to be selectively coupled between a voltage node and a metering line that communicates a signal indicative of status of a flow line through which a metered substance flows. An impedance of the pull up circuit is set to reduce power consumption based on a calibration, and the pull up circuit can be disabled between sampling of the signal to reduce power consumption.

Low power metering using pulse counting

An LCD controller includes at least one I/O pad for providing an LCD drive voltage in an LCD mode of operation. I/O pad logic drives the at least one I/O pad responsive to a provided bias voltage. Voltage selection logic selects a higher voltage between an LCD drive voltage and an externally provided system voltage as a first voltage. Bias voltage logic selects one of the system voltage or the first voltage as the bias voltage for the I/O pad logic. The system voltage is selected as the bias voltage for the I/O pad logic in a non-LCD mode of operation for the I/O pad and the first voltage is selected for the bias voltage for the I/O pad logic in the LCD mode of operation for the I/O pad.

System and method for providing bias voltages to pad logic of an LCD controller

A LINBUS communication network comprises a microcontroller unit containing processing circuitry for performing predefined digital processing functions. LINBUS communication network hardware is located within the microcontroller unit for digitally communicating with an off-chip LINBUS device for transmitting data thereto and receiving data therefrom. A plurality of LINBUS communication network interfaces selectively connects one of a plurality of groups of slave devices to the LINBUS network communications hardware.

System and method for connecting a master device with multiple groupings of slave devices via a LINBUS network

An apparatus comprises a band gap voltage generator circuit for generating a band gap voltage. A temperature invariant current generator is located within the band gap voltage generator circuit for generating a temperature invariant current. A temperature invariant current correction circuit is located within the band gap voltage generator circuit and adjusts the output voltage responsive to the temperature invariant current without altering temperature characteristics of the temperature invariant current.

Band gap generator with temperature invariant current correction circuit

A method for coding a digital to analog converter of a successive approximation register analog to digital converter includes the steps of first switching capacitors associated with a bit from ground to a reference voltage. Next, a determination is made of whether a logical value of the bit is a first or a second value. If the logical value is the first value, capacitors associated with a next bit are switched from ground to a reference voltage. If the logical value is the second value, one half of the capacitors associated with the bit currently connected are switched from the reference voltage to ground.

Coding method for digital to analog converter of a SAR analog to digital converter

A reconfigurable processor includes a processor core for operating on a set of instructions to carry out predefined processes and includes a plurality of input/output pins in addition to a plurality of functional input/output blocks. These functional blocks allow the processing core to interface with the plurality of input/output pins, each of the functional input/output blocks having an associated and predetermined functionality. This functionality comprises the output as a function of the input, the function defined by the functionality. Each of the functional input/output blocks has a requirement for a defined number of the plurality of input/output pins wherein the total of the defined number for all of the plurality of functional input/output blocks exceeds the number of the plurality of input/output pins and wherein the processor core is interfaced with one of the input or output of each of the functional blocks. A reconfigurable interface selectively interfaces between the other of the input or output of the functional blocks and a select one or ones of the plurality of input/output pins, such that the processor core can be interfaced with the select one or ones of the input/output pins. The reconfigurable interface is operable to define how each of the plurality of input/output pins interfaces with the select ones of the plurality of functional blocks and the associated functionality in accordance with configuration information. A non-volatile memory is provided for storing information for use in association with the configuration information, such that the stored information can be altered.

Reconfigurable interface for coupling functional input/output blocks to limited number of I/O pins

An integrated circuit package includes a processing core for operating on a set of instructions to carry out predefined processes. A plurality of comparators perform compare operations within the integrated circuit package. At least one control register is associated with each of the plurality of comparators, and each of the plurality of comparators are software programmable to control a hysteresis of the comparators responsive to control bits established in the at least one control register of the comparator by the processing core. An amount of positive hysteresis is programmed via a first group of the control bits and an amount of negative hysteresis is programmed via a second group of the control bits.

Comparators in IC with programmably controlled positive / negative hysteresis level and open-drain / push-pull output coupled to crossbar switch or rising / falling edge interrupt generation

A system and method for an anti-pinch powered window system includes a window and a mechanical drive mechanism for raising and lowering the window. An electric motor drives the mechanical drive mechanism responsive to a command. A microcontroller unit generates the command responsive to a measured load current of the electric motor. A command to change direction of the window is generated responsive to a determination that the measured load current has exceeded a variable threshold level indicating that the window has stopped due to an obstruction. The variable threshold level is determined by the load current data stored within a memory.

System and method for controlling anti-pinch powered windows

An integrated circuit package includes a processing core and an internal oscillator. The processing core operates on a set of instructions to carry out predefined processes. The internal oscillator provides a system clock for the integrated circuit package. The internal oscillator has associated therewith an internal control register for controlling the operation of the internal oscillator responsive to control bits of the internal oscillator controlled by the processing core.

Integrated circuit package including programmable oscillators

Growing community of inventors

Austin, TX, United States of America

Douglas S Piasecki