International Business Machines Corporation

Douglas S Armbrust

Timothy Dooling Sullivan

William F Clark, Jr

William Thomas Motsiff

Eric Jeffrey White

William A Klaasen

Margaret L Gibson

Laura Serianni

Jed Hickory Rankin

Arne Watson Ballantine

Roger W Cheek

Dale Warner Martin

Michael B Rice

Doreen D DiMilia

Mark L Reath

Sylvia R Tousley

John M Baker

A method and apparatus are provided for controlling a CVD process used to deposit films on semiconductor substrates wherein the by-products of the reaction are measured and monitored during the reaction preferably using mass spectrometry and the results used to calculate the concentrations of the by-products and to control the CVD reaction process based on the by-product concentrations. An exemplary CVD process is the deposition of tungsten metal on a semiconductor wafer. A preferred method and apparatus uses a capillary gas sampling device for removing the by-product gases of the reaction as a feed for the mass spectrometer. The capillary gas sampling device is preferably connected to a differential pump.

In-situ monitoring of chemical vapor deposition process by mass spectrometry

A method for forming a semiconductor structure includes supplying a structure having an exposed last metalization layer, cleaning the last metalization layer, forming a silicide in a top portion of the last metalization layer and forming a terminal over the silicide.

Self-aligned copper silicide formation for improved adhesion/electromigration

Semiconductor chip structures are provided with embedded thermal conductors for removing heat from one or more electrically conductive circuit members thereof, wherein the circuit members are formed on one or more dielectric layers above a substrate, each layer having a low dielectric constant and a low thermal conductivity. One or more cooling posts, for example, multiple thermally conductive plugs, are selectively disposed within the semiconductor chip structure adjacent to one or more electrically conductive members and thermally coupled thereto so that heat produced by the members is transferred into and through the cooling posts for forwarding to the substrate and/or to an upper surface of the semiconductor chip structure. The backside of the substrate has a thermal sink thermally coupled thereto and electrically isolated from the substrate. The thermal sink includes one or more thermally conductive via structures embedded within the substrate and aligned to thermally contact to the cooling posts disposed above the substrate.

Semiconductor chip structures with embedded thermal conductors and a thermal sink disposed over opposing substrate surfaces

A method to define and tailor process limited lithographic features is provided. The method may be used to form sub lithographic spaces between features on a semiconductor wafer. A mask is formed and patterned on the wafer. Spacers are formed on sidewalls of the mask. The pattern of the mask and spacers is then transferred to an underlying layer.

Method to define and tailor process limited lithographic features using a modified hard mask process

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Gloucester, MA, United States of America

Douglas S Armbrust