National Semiconductor Corporation

Douglas Robert Farrenkopf

Richard B Merrill

Kevin E Brehmer

Philip J Cacharelis

Kamesh V Gadepally

Vladislav Vashchenko

Jayendar Rajagopalan

Christopher Falvey

A three-terminal snapback device is utilized with a control circuit to provide a low snapback voltage that is protected from non-ESD voltage spikes and ripples. In response to a fast edge, the control circuit lowers the snapback voltage, unless a status signal indicates that normal operating voltages are present, and raises the snapback voltage a predefined time later. If the fast edge represents an ESD pulse, SCR operation is initiated at the lowered snapback voltage. If the fast edge represents a power on sequence, the maximum voltage is less than the momentarily lowered snapback voltage and therefore insufficient to initiate SCR operation. Further, once normal operating voltages are present, the control circuit continuously maintains the raised snapback voltage so that a non-ESD voltage spike or ripple can not improperly turn on the snapback device.

ESD protection circuit with a low snapback voltage that is protected from fast non-ESD voltage spikes and ripples

A method and system for providing startup delay is disclosed. The system includes a startup delay circuit. The startup delay circuit includes a signal generating sub-circuit that generates an output signal. The signal generating sub-circuit generates the output signal after a period of time that is related to an input offset of a component of the signal generating sub-circuit.

Method and system for providing startup delay

A pad that experiences a high-voltage, high dV/dT signal during normal operation is prevented from falsely triggering by utilizing a bipolar transistor connected to the pad to provide ESD protection, and a MOS transistor connected to the bipolar transistor to turn off the bipolar transistor during normal circuit operation.

ESD protection circuit for high-voltage, high DV/DT pads

A bootstrap capacitor low voltage prevention circuit and method to control the same is provided. When a low voltage situation is detected the bootstrap capacitor is charged. An over voltage protection circuit is included that prevents the circuit from staying in an over voltage situation for a long period of time.

Bootstrap capacitor low voltage prevention circuit

An apparatus and method that enforces current sharing and provides low on times for a multiphase voltage mode regulator has been described. A current level is sensed for each leg of the multiphase regulator. The sensed current level relates to the inductor current level for each of the phases. An average current level is determined from the sensed current levels. A comparison is then made between the sensed current levels and the average current level. In response to the comparison, the current level for the leg is adjusted. According to one embodiment, the on time for the switch of the phase is adjusted. The switch is adjusted to a shorter or longer time when the phase signal level is not equal to the average current level. The apparatus and method work with as few as 2-phases, or as many as N-phases.

Multiphase switching regulator control architecture for low on time systems that enforces current sharing

A DC-to-DC converter which includes a current mode switching controller or regulator chip (which includes an oscillator producing a ramped voltage which periodically increases at a fixed ramp rate), circuitry including a current sense resistor external to the integrated circuit controller, and ramp adjustment circuitry (including at least one element external to the integrated circuit controller) which sets the effective ramp rate of the oscillator's ramped voltage. The external element of the ramp adjustment circuitry can be a resistor or a capacitor, or circuitry comprising both a resistor and capacitor. Another aspect of the invention is a DC-to-DC conversion method using a current mode switching controller or regulator chip (controller chip) including an oscillator which produces a ramped voltage, and external circuitry (coupled to the controller chip) including a current sense resistor across which a feedback voltage is developed, including the steps of operating the controller chip to switch on the power switch periodically and switch off the power switch at times determined by comparison of a feedback signal indicative of the feedback voltage and an adjustment voltage, with a reference signal indicative of the ramped voltage and a reference potential, where comparison of the feedback signal with the reference signal is effectively comparison of the feedback voltage with the difference between the reference potential and an effective ramped voltage determined by the ramped voltage and the adjustment voltage; and developing the adjustment voltage across at least one adjustment element external to the controller chip such that the adjustment voltage varies in phase with the ramped voltage and periodically increases at a fixed adjustment rate determined by the at least one adjustment element.

DC-to-DC converter with current mode switching controller that produces ramped voltage with adjustable effective ramp rate

A method and circuit which employs negative feedback to generate a ramped voltage having well controlled maximum amplitude. In preferred embodiments, the invention is an integrated circuit (or portion of an integrated circuit) which generates a ramped voltage with controlled maximum amplitude in a manner independent of process and temperature variations in implementing and operating the circuit. Preferably, the circuit includes an amplifier having an input coupled to receive a reference signal, an output coupled to ramped voltage generator, and another input coupled to the output of the ramped voltage generator, thus implementing a negative feedback loop in which the amplifier asserts feedback to control the maximum amplitude of the ramped voltage generated by the ramped voltage generator. Preferably, the ramped voltage generator periodically charges and discharges a capacitor to generate the ramped voltage, the amplifier is a transconductance amplifier which is periodically enabled (for a portion of each charging cycle of the capacitor) in response to a clock signal, a one-shot circuit produces a delayed voltage pulse train in response to the clock signal, and the ramped voltage generator receives the delayed voltage pulse train and discharges the capacitor in response to each pulse of the delayed voltage pulse train.

Method and apparatus using feedback to generate a ramped voltage with controlled maximum amplitude

A circuit having multiple channels for generating multiple ramped voltage signals (preferably of a type useful in an interleaved PWM dc/dc converter) such that each ramped voltage signal has a different phase, and all the ramped voltage signals have a uniform controlled maximum amplitude. The circuit can be implemented as an integrated circuit (or portion of an integrated circuit) which generates the multiple ramped voltage signals with uniform maximum amplitude in a manner independent of process and temperature variations in implementing and operating such integrated circuit. In preferred embodiments, the circuit includes a single amplifier having an input coupled to receive a reference signal (indicative of a preselected maximum ramped voltage amplitude) and an output which is coupled (in time-division-multiplexed fashion) to each of the ramped voltage generation channels, thus implementing time-division-multiplexed negative feedback loops which control the maximum amplitude of the ramped voltage signal generated by each channel. The input offset voltage error of the amplifier is applied across all channels equally. Preferably, the ramped voltage signal generating circuit also includes circuitry for generating clock signals for controlling generation of the ramped voltage signals. Another aspect of the invention is a method for generating multiple ramped voltage signals (preferably those of a type useful in an interleaved PWM dc/dc converter) such that each ramped signal has a different phase and a uniform, controlled maximum amplitude.

Circuit for generating interleaved ramped voltage signals having

A DC-to-DC converter which includes a switching controller or regulator (implemented as an integrated circuit) and circuitry external to the controller or regulator chip, where the controller or regulator chip includes soft start circuitry but requires no component external thereto (other than the external circuitry present in DC-to-DC converters having no soft start capability) in order to accomplish a soft start. The invention is especially useful where it is impractical or undesirable to implement the controller or regulator chip with a pin dedicated for connection to an external soft start capacitor or other component or circuit for performing a soft start operation. Other aspects of the invention are a controller or regulator chip for use in such a converter, and a method for performing DC-to-DC conversion using such a switching controller or regulator chip and external circuitry coupled to the controller or regulator chip to generate an output potential which increases to a regulated value during a soft start period and remains at the regulated value during steady state operation. Preferably, the controller or regulator chip includes an on-board capacitor, charging circuitry for charging the capacitor during a soft start period, an overvoltage comparator which compares the voltage across the capacitor with a feedback potential (proportional to the output potential of a DC-to-DC converter with which the controller or regulator chip is used), and an OR gate having a first input coupled to receive the output of the comparator and a second input coupled to receive a reset signal which (during steady state operation of the controller or regulator chip) triggers the switching off of the converter's power transistor.

Switching controller chip with internal but not external soft start

A switching controller or regulator (implemented as an integrated circuit) which is operable in any selected one of multiple two modes, including an oscillator mode in which it generates switch control signals for turning on a power switch in response to internally generated clock pulses, a sync mode in which it generates the switch control signals in response to pulses supplied from external circuitry, and preferably also a shutdown mode in which it consumes little or no power and does not generate switch control signals. In the oscillator and sync modes, the controller or regulator also generates additional control signals for turning off the power switch each time after it is turned on, so as to regulate the duty cycle of the power switch. Preferably, the controller or regulator chip has only a single external pin for receiving control signals for causing the chip to enter a sequence of the available operating modes, and it includes a level shifter, a sync timer, a shutdown timer, and a controllable oscillator, all connected to such pin. A multiplexer, operating under control of the sync timer, receives the outputs of the level shifter and oscillator, and selects one of these outputs in response to a control signal from the sync timer. Other aspects of the invention are a DC-to-DC converter including a switching controller or regulator chip of the described type and circuitry external to the chip for generating a regulated output potential in response to an input potential, and a method for performing DC-to-DC conversion using any embodiment of the switching controller or regulator chip.

Switching controller chip operable in selected ones of multiple power

Integrated circuits suitable for high-performance applications, especially mixed signal products that have analog and digital sections, are fabricated from a semiconductor structure in which lower buried regions of opposite conductivity types are situated along a lower semiconductor interface between a semiconductive substrate and an overlying lower semiconductive layer. An upper buried region of a selected conductivity type is situated along an upper semiconductor interface between the lower semiconductive layer and an overlying upper semiconductive layer. Another upper buried region of opposite conductivity type to the first-mentioned upper buried region is preferably situated along the upper semiconductor interface. The upper semiconductive layer contains P-type and N-type device regions in which transistor zones are situated. The semiconductor structure is configured so that at least one of each of the P-type and N-type device regions is electrically isolated from the substrate. Complementary bipolar transistors can be integrated with complementary field-effect transistors in the structure.

Fabrication of semiconductor structure having two levels of buried

Integrated circuits suitable for high-performance applications, especially mixed signal products that have analog and digital sections, are fabricatable from a semiconductor structure having two levels of buried regions. In a typical embodiment lower buried regions of opposite conductivity types are situated along a lower semiconductor interface between a semiconductive substrate and an overlying lower semiconductive layer. Upper buried regions of opposite conductivity type are similarly situated along an upper semiconductor interface between the lower semiconductive layer and an overlying upper semiconductive layer. The upper semiconductive layer contains P-type and N-type device regions in which transistor zones are situated. The semiconductor structure is normally configured so that at least one of each of the P-type and N-type device regions is electrically isolated from the substrate. Complementary bipolar transistors can be integrated with complementary field-effect transistors in the structure.

Semiconductor structure having two levels of buried regions

In a method of fabricating a DMOS transistor structure, wherein the DMOS transistor structure includes an active semiconductor substrate region having a tub of N-type conductivity formed therein, the N-type tub being formed over an N.sup.+ buried region, and having an N.sup.+ sinker region formed therein at an edge of the N-type tub, the N.sup.+ sinker region extending from a surface of the N-type tub to the N.sup.+ buried region, a pad oxide layer is formed on the N-tub and on the N.sup.+ sinker region. A composite mask is then formed on the silicon nitride layer, and includes etched openings such that the surface of the periphery of the N-type tub is exposed and the interface between the N-type tub and the N.sup.+ sinker region is exposed. The composite mask is then utilized to form field oxide isolation regions in the semiconductor substrate region at the periphery of the N-type tub and at the interface between the N-type tub and the N.sup.+ sinker region. After removing the composite mask, a P-body mask is formed on the nitride layer. Finally, a metal layer is formed over the structure resulting from the above-defined steps to form metal contacts to the P-body region, the gate contact and the N.sup.+ sinker region.

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Campbell, CA, United States of America

Douglas Robert Farrenkopf