Via Alliance Semiconductor Co., Ltd.

Centaur Technology, Inc.

Shanghai Zhaoxin Semiconductor Co., Ltd.

Via Technologies, Inc.

Douglas Raye Reed

Rodney E Hooker

G Glenn Henry

Terry J Parks

Colin Eddy

John Michael Greer

Al Loper

Stephan Gaskins

Albert J Loper

Kim C Houck

Parviz Palangpour

Jason Chen

Akarsh Dolthatta Hebbar

Albert J Lopez

In one embodiment, a controller in a microprocessor, the controller configured to manage accesses to dynamic random access memory (DRAM), the controller comprising: a first table configured to track cache lines that have been written to zero for a plurality of first memory regions; and a second table configured to track the cache lines that have been written to zero for a plurality of second memory regions, wherein each of the plurality of second memory regions comprises a group of the plurality of first memory regions where all of the cache lines within each of the plurality of the first memory regions within the group have been written to zero.

Refreshing cache regions using a memory controller and multiple tables

In one embodiment, a method of selectively reserving portions of a last level cache (LLC) for a multi-core processor, the method comprising: allocating, by an executive system, plural classes of service to the portions of the LLC, wherein the portions comprise ways, and wherein each of the plural classes of service are allocated to one or more of the ways; assigning, by the executive system, one of the plural classes of service to an application as a default class of service, wherein the assignment controls which of the ways the application can allocate into; and overriding, by the application, the default class of service to enable allocation by the application to the one or more of the ways associated with a non-default class of service.

Cat aware loads and software prefetches

In one embodiment, a bounding box prefetch unit in a microprocessor, the bounding box prefetch unit comprising: storage comprising a plurality of active prefetcher state entries for storing state information for a corresponding plurality of access streams associated with load requests, and a corresponding plurality of prediction logic; and a prefetcher state cache comprising plural prefetcher state entries that do not match any of the active prefetcher state entries.

Prefetch state cache (PSC)

In one embodiment, a prefetching method implemented in a microprocessor, the prefetching method comprising: issuing all prefetches remaining for a memory block as L3 prefetches based on a set of conditions; and issuing L2 prefetches for cache lines corresponding to the L3 prefetches upon reaching the end of the memory block.

Bounding box prefetcher

In one embodiment, a microprocessor, comprising: plural cores, each of the cores comprising a level 1 (L1) cache and a level 2 (L2) cache; and a shared level 3 (L3) cache comprising plural L3 tag array entries, wherein a first portion of the plural L3 tag array entries is associated with data and a second portion of the plural L3 tag array entries is decoupled from data, wherein each L3 tag array entry comprises tag information and data zero information, the data zero information indicating whether any data associated with the tag information is known to be zero or not.

Zero bits in L3 tags

In one embodiment, a microprocessor, comprising: a first data cache; and a second data cache configured to process both a miss in the first data cache resulting from a first load or store operation and an eviction from the first data cache to accommodate the first load or store operation, the second data cache configured to indicate to the first data cache that the eviction is complete before the eviction is actually complete based on a first state corresponding to the eviction.

L1D to L2 eviction

A processor including a memory controller for interfacing an external memory and a programmable functional unit (PFU). The PFU is programmed by a PFU program to modify operation of the memory controller, in which the PFU includes programmable logic elements and programmable interconnectors. For example, the PFU is programmed by the PFU program to add a function or otherwise to modify an existing function of the memory controller enhance its functionality during operation of the processor. In this manner, the functionality and/or operation of the memory controller is not fixed once the processor is manufactured, but instead the memory controller may be modified after manufacture to improve efficiency and/or enhance performance of the processor, such as when executing a corresponding process.

Processor with memory controller including dynamically programmable functional unit

A hardware processing unit is provided. The hardware processing unit includes: an accumulator; a multiplier-adder receives first and second factors and receives an addend, the multiplier-adder generates a sum of the addend and a product of the first and second factors and provides the sum; a first multiplexer receives a first operand, a positive one, and a negative one and selects one of them for provision as the first factor to the multiplier-adder; a second multiplexer receives a second operand, a positive one, and a negative one and selects one of them for provision as the second factor to the multiplier-adder; a third multiplexer, having an output, that receives the first operand and the second operand and selects one of them for provision on its output; and a fourth multiplexer receives the third multiplexer output and the sum and selects one of them for provision to the accumulator.

Neural network unit

A first data storage holds cache lines, an accelerator has a second data storage that selectively holds accelerator data and cache lines evicted from the first data storage, a tag directory holds tags for cache lines stored in the first and second data storages, and a mode indicator indicates whether the second data storage is operating in a first or second mode in which it respectively holds cache lines evicted from the first data storage or accelerator data. In response to a request to evict a cache line from the first data storage, in the first mode the control logic writes the cache line to the second data storage and updates a tag in the tag directory to indicate the cache line is present in the second data storage, and in the second mode the control logic instead writes the cache line to a system memory.

Processor with selective data storage (of accelerator) operable as either victim cache data storage or accelerator memory and having victim cache tags in lower level cache wherein evicted cache line is stored in said data storage when said data storage is in a first mode and said cache line is stored in system memory rather then said data store when said data storage is in a second mode

A cache stores 2{circumflex over (&#x2003;)}J-byte cache lines has an array of 2{circumflex over (&#x2003;)}N sets each holds tags each X bits and 2{circumflex over (&#x2003;)}W ways. An input receives a Q-bit address, MA[(Q&#x2212;1):0], having a tag MA[(Q&#x2212;1):(Q&#x2212;X)] and index MA[(Q&#x2212;X&#x2212;1):J]. Q is at least (N+J+X&#x2212;1). Set selection logic selects one set using the index and tag LSB; comparison logic compares all but the LSB of the tag with all but the LSB of each tag in the selected set and indicates a hit if a match; allocation logic, when the comparison logic indicates there is not a match: allocates into any of the 2{circumflex over (&#x2003;)}W ways of the selected set when operating in a first mode; and into a subset of the 2{circumflex over (&#x2003;)}W ways of the selected set when operating in a second mode. The subset of is limited based on bits of the tag portion.

Multi-mode set associative cache memory dynamically configurable to selectively allocate into all or a subset of its ways depending on the mode

A cache memory comprising: a mode input indicates in which of a plurality of allocation modes the cache memory is to operate; a set-associative array of entries having a plurality of sets by W ways; an input receives a memory address comprising: an index used to select a set from the plurality of sets; and a tag used to compare with tags stored in the entries of the W ways of the selected set to determine whether the memory address hits or misses; and allocation logic, when the memory address misses in the array: selects one or more bits of the tag based on the allocation mode; performs a function, based on the allocation mode, on the selected bits of the tag to generate a subset of the W ways of the array; and allocates into one way of the subset of the ways of the selected set.

Dynamic cache replacement way selection based on address tag bits

A processor comprising a mode indicator, a plurality of processing cores, and a neural network unit (NNU), comprising a memory array, an array of neural processing units (NPU), cache control logic, and selection logic that selectively couples the plurality of NPUs and the cache control logic to the memory array. When the mode indicator indicates a first mode, the selection logic enables the plurality of NPUs to read neural network weights from the memory array to perform computations using the weights. When the mode indicator indicates a second mode, the selection logic enables the plurality of processing cores to access the memory array through the cache control logic as a cache memory.

Processor with memory array operable as either cache memory or neural network unit memory

A processor with an expandable instruction set architecture for dynamically configuring execution resources. The processor includes a programmable execution unit (PEU) that may be programmed to perform a user-defined function in response to a user-defined instruction (UDI). The PEU includes programmable logic elements and programmable interconnectors that are collectively programmed to perform at least one processing operation. A UDI loader is responsive to a UDI load instruction that specifies a UDI and a location of programming information that is used to program the PEU. The PEU may be programmed for one or more UDIs for one or more processes. An instruction table stores each UDI and corresponding information to identify the UDI and possibly to reprogram the PEU if necessary. A UDI handler consults the instruction table to identify a received UDI and to send corresponding information to the PEU to execute the corresponding user-defined function.

Processor with an expandable instruction set architecture for dynamically configuring execution resources

A processor comprising a plurality of processing cores, a last level cache memory (LLC) shared by the plurality of processing cores, and a neural network unit (NNU) comprising an array of neural processing units (NPU) and a memory array. The LLC comprises a plurality of slices. To transition from a first mode in which the memory array operates to store neural network weights read by the plurality of NPUs to a second mode in which the memory array operates as a slice of the LLC in addition to the plurality of slices, the processor write-back-invalidates the LLC and updates a hashing algorithm to include the memory array as a slice of the LLC in addition to the plurality of slices. To transition from the second mode to the first mode, the processor write-back-invalidates the LLC and updates the hashing algorithm to exclude the memory array from the LLC.

Processor with memory array operable as either last level cache slice or neural network unit memory

A processor comprises a neural network unit (NNU) and a processing complex (PC) comprising a processing core and cache memory. The NNU comprises neural processing units (NPU), cache control logic (CCL) and a memory array (MA). To transition from a first mode in which the MA operates to hold neural network weights for the array of NPUs to a second mode in which the MA and CCL operate as a victim cache, the CCL begins to cache evicted cache lines into the MA in response to eviction requests and begins to provide to the PC lines that hit in the MA in response to load requests. To transition from the second mode to the first mode, the CCL invalidates all lines of the MA, ceases to cache evicted lines into the MA in response to eviction requests, and ceases to provide to the PC lines in response to load requests.

Growing community of inventors

Austin, TX, United States of America

Douglas Raye Reed