Motorola Corporation

Freescale Semiconductor,inc.

Douglas R Roberts

Eric D Luckowski

Bradley M Melnick

Shahid Rauf

Peter L G Ventzek

Bruce E White

Bo Jiang

Ko-Min Chang

Robert E Jones

Kuo-Tung Chang

Wei-Ming Chen

Gary L Huffman

Keith Forbes

A method for forming a capacitor includes providing a metal-containing bottom electrode, forming a capacitor insulator over the metal-containing bottom electrode, forming a metal-containing top electrode over the capacitor insulator, and forming a dielectric-containing field modification layer over the capacitor insulator and at least partially surrounding the metal-containing top electrode. Forming the dielectric-containing field modification layer may include oxidizing a sidewall of the metal-containing field modification layer. A barrier layer may be formed over the capacitor insulator prior to forming the metal-containing top electrode.

Thin-film capacitor with a field modification layer

Thin-film capacitor with a field modification layer and methods for forming the same

A MIM capacitor is formed over one or more metal interconnect layers in a semiconductor device. The capacitor has a lower plate electrode and an upper plate electrode. An insulator is formed between the plate electrodes. Prior to forming the first plate electrode a first insulating layer is deposited over the metal of an interconnect layer. The first insulating layer is planarized using a chemical mechanical polish (CMP) process. A second insulating layer is then deposited over the planarized first insulating layer. The first plate electrode is formed over the second insulating layer. An insulator is formed over the first plate electrode and functions as the capacitor dielectric. A second plate electrode is formed over the insulator. Planarizing the first insulating layer and depositing a second insulating layer over the first insulating layer, reduces defects and produces a more reliable capacitor.

MIM capacitor in a semiconductor device and method therefor

A process for forming a metal-insulator-metal (MIM) capacitor structure includes forming a recess in the dielectric layer ( ) of a semiconductor substrate ( ). A first capacitor electrode ( ) is formed in the recess having a copper first metal layer ( ) with a conductive oxidation barrier ( ) formed over the first metal layer ( ). The first capacitor electrode ( ) is planarized relative to the dielectric layer ( ). An insulator ( ) is formed over the first capacitor electrode ( ) and a second capacitor electrode ( ) is formed over the insulator ( ). Forming the first capacitor electrode ( ) in the recess maintains the alignment of a periphery of the copper first metal layer ( ) with the conductive oxidation barrier ( ).

Process for making a MIM capacitor

A dielectric film (,) is formed overlying a semiconductor device substrate (,). A dielectric post (,) having an outer peripheral boundary having sidewalls is formed over the dielectric film (,). A first conductive film (,) is deposited at least along the sidewalls of the dielectric post (,) to form a lower electrode. A capacitor dielectric film (,) is deposited on the first conductive film, and a upper electrode (,) is formed on the capacitor dielectric film (,).

Capacitor electrode having conductive regions adjacent a dielectric post

A dielectric film (110) is formed overlying a semiconductor device substrate (10). A dielectric post (204) having an outer peripheral boundary having sidewalls is formed over the dielectric film (110). A first conductive film (402) is deposited at least along the sidewalls of the dielectric post (204) to form a lower electrode. A capacitor dielectric film (1801) is deposited on the first conductive film, and a upper electrode (1802) is formed on the capacitor dielectric film (1801).

Method for forming a capacitor structure

The present invention is a process for forming a lower capacitor electrode. Specifically, an oxygen tolerant bottom electrode layer (312) is formed over a conductive plug (216). A dielectric layer (420) is deposited and partially removed in order to form an inlaid bottom electrode structure. A capacitor dielectric (810) such as BST is formed over the lower electrode (310). The upper electrode (812) is formed over the capacitor dielectric (810) and the resulting stack is patterned in order to form a final capacitive device (916). In another embodiment of the present invention, a hardmask is formed over the bottom electrode (310) and removed prior to the capacitor dielectric (810) being formed.

Method of forming a semiconductor device having a stacked capacitor

An EEPROM device includes a split-gate FET (10) having a source (36), a drain (22), a select gate (16) adjacent the drain (22), and a control gate (32) adjacent the source (36). When programming the split-gate FET (10), electrons are accelerated in a portion of a channel region (38) between the select gate (16) and the control gate (32), and then injected into a nitride layer (24) of an ONO stack (25) underlying the control gate (32). The split-gate FET (10) is erased by injecting holes from the channel region (38) into the charge nitride layer (24). When reading data from the split-gate FET (10), a reading voltage is applied to the drain (22) adjacent the select gate (16). Data is then read from the split-gate FET (10) by sensing a current flowing in a bit line coupled to the drain (22).

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Austin, TX, United States of America

Douglas R Roberts