Silicon Laboratories Inc.

Other

Analog Devices,inc.

Solid State Chargers, Inc.

Douglas R Frey

Ramin Khoini-Poorfard

Michael James Mills

Philip K Hoffman

Jeffrey Lee Sonntag

Russell J Apfel

Marius Goldenberg

Ion Constantin Tesu

David M Pietruszynski

Riad S Wahby

András Vince Horvath

Anantha Nag Nemmani

Siddharth Sundar

Geoffrey Thompson

Patrick Copley

An analog signal is transported across an isolation channel using edge modulation/demodulation of a pulse width modulated (PWM) signal. An edge modulator is responsive to rising edges of the PWM signal to generate first pulses having a first predetermined pulse width and is responsive to receipt of falling edges of the PWM signal to generate second pulses having a second predetermined pulse width with the same polarity as the first pulses. On the opposite side of the isolation channel an edge demodulating circuit recreates the PWM signal using the first and second pulses. The rise and falling edges of the PWM signals can be distinguished based on the pulse width of the first and second pulses. A second order pulse width modulator may be used to generate the PWM signal.

Transport of an analog signal across an isolation barrier

One embodiment of an apparatus for switching a transistor includes a first current mirror providing i=Ki, as a transistor base current, wherein the first current mirror is selectively driven by a current source A second current mirror providing a feedback signal i=Kito the first current mirror such that wherein icontributes to the transistor collector current, wherein i=i&#x2212;KKi.

Power supply with digital control loop

A phase-locked loop (PLL) achieves initial lock using a course fractional-N divider driving a binary phase detector. Once frequency lock is achieved, this divider may be turned off, while an adaptive phase detector takes over control of the PLL front end. The adaptive phase detector (APD) receives input directly from the VCO and the reference clock, deriving digital control signals and a precision phase detector output. The APD operates at the update rate, generating a digital delta sigma modulator (DSM) data stream output at the update rate. The APD automatically locks to a digitally generated ramp corresponding to an expected difference between the VCO output and the reference clock, while adaptively correcting for DC errors and ramp cancellation errors.

Dividerless PLL architecture

A linear amplifier architecture includes first, second, and third stages. The first stage is a transconductance stage. The third stage is a current amplification stage. The second stage is an interfacing stage between the first and third stages. The interfacing stage provides a voltage bias and a current to the third stage. The linear amplifier is a class AB amplifier. Quiescent currents for the output devices of the third stage are controlled by the second stage. The stages may be fabricated on the same semiconductor substrate. In one embodiment, the amplifier is fabricated as a complementary metal oxide semiconductor (CMOS) integrated circuit using metal oxide semiconductor field effect transistors (MOSFET). In one application, the amplifier serves as a component of a driver circuit for a subscriber line. Electrostatic discharge (ESD) protection circuitry provided for the amplifier may also be suitable for other applications. In various embodiments, the ESD circuitry enables dynamic clamping of the output devices without introducing undesirable capacitive coupling during normal circuit operation.

Integrated driver circuitry

A digital-to-analog converter circuit for a subscriber line analog front end includes a differential amplifier, switch circuitry, and first and second current steering digital-to-analog converters (DAC), each DAC having a first and second output forming a differential DAC output. The switch circuitry couples the differential output of at most a selected one of the first and second DACs to a pair of switch nodes. When the differential output of the selected DAC is coupled to the pair of switch nodes, the differential output of the other DAC is shorted. A differential input of the differential amplifier is communicatively coupled to the pair of switch nodes. A differential output of the differential amplifier is coupled to drive a tip line and a ring line of a subscriber line. In various embodiments, the DACs, switch circuitry, and differential amplifier reside on the same semiconductor substrate.

Digital-to-analog converter switching circuitry

A method of tuning a DCXO includes the step of providing a coarse tuning array and a fine tuning array of capacitors fabricated on the same integrated circuit die. The coarse array is adjusted until the difference between a desired frequency and the output frequency corresponds to a change in capacitance no greater than half the range of the fine tuning array. In one embodiment, the fine tuning array is adjusted to mid-range before adjusting the coarse tuning array. A DCXO apparatus includes at least one integrated circuit segmented switched capacitor network providing a capacitance that is a nonmonotonic function of a composite input code. The segmented switched capacitor network includes parallel coupled binary weighted and thermometer coded switched capacitor networks for coarse and fine tuning, respectively.

Digitally controlled crystal oscillator with integrated coarse and fine control

A digital-to-analog conversion circuit includes first and second DACs. Switch circuitry couples a selected output of only one of the DACs to an output node at any given time. In one embodiment, a second output of the first DAC is coupled to the first output of the second DAC at a common node. The first output of the first DAC is coupled to a first switch node and a second output of the second DAC is coupled to a second switch node. A first switch couples the common node to the first switch node in response to a first switch signal. A second switch couples the common node to the second switch node in response to a second switch signal. The switch signals ensure that the common node is coupled through the first and second switches to only one of the first and second switch nodes at any given time.

A signal conditioning circuit compresses an audio signal by producing a gain signal that is a function of the time-averaged audio signal and a compression ratio, and amplifying the audio signal by an exponential function of the gain signal. The conditioning circuit merges the functions of buffering the audio signal and producing a full-wave rectified version of the audio signal into a single buffer circuit. An averaging circuit generates a time-averaged signal in response to the full-wave rectified signal. An interface circuit includes downward expansion, compression and limiting circuits for scaling the time-averaged signal with a low compression ratio when it is less than a break point, with a selected compression ratio when it is between the break point and a rotation point, and with a high compression ratio when it exceeds the rotation point. The interface circuit produces the gain signal in response to the time-averaged signal and the corresponding compression ratio. A voltage controlled amplifier amplifies the buffered input signal by an exponential function of the gain signal to produce a compressed output signal.

Signal conditioning circuit for compressing audio signals

An explicit RMS detector sequentially performs the square, mean and square-root operations in the log domain. An input signal is first applied to a log converter, and then to a times two multiplier which squares the input signal. A log filter averages the log square input signal for a predetermined period to approximate the 'mean' operation, after which a times one-half multiplier operates on the log mean-square input signal to compute the square root. An exponentiator exponentiates the resulting log root-mean-square input signal to produce an output signal that approximates the RMS value of the input signal for the predetermined period.

Explicit log domain root-mean-square detector

A current mode VCA includes a negative feedback architecture around a gain core stage. An input signal is injected as a differential current into the signal path and is converted to a differential voltage by a transresistance stage having a dynamic impedance. The differential voltage is applied to a transconductance stage which limits the VCA's high frequency gain and stabilizes the feedback loop. The transconductance stage supplies a differential drive current to the gain core stage, which produces two differential output currents that sum to the differential drive current. The fraction of the drive current provided to each output current is controlled by the application of a control signal to the gain core stage. A current-to-voltage converter produces an output voltage in response to the output current. A differential feedback current is returned to the transresistance stage to complete the negative feedback loop and control the dynamic impedance of the transresistance stage to compensate for the gain extracted from the VCA and maintain constant loop gain.

Voltage controlled amplifier

A battery charger of the driven blocking oscillator type includes a three-winding transformer. The primary winding is connected in series with the collector-emitter path of a switching transistor. The secondary winding is connected in series with the collector-emitter path of a sense transistor which responds to the current flowing through the switching transistor. The tertiary winding is connected in series with the battery, series-connected batteries or series-connected battery packs sought to be recharged, via a diode, which may be connected in parallel with a capacitor. No smoothing capacitor is provided across the battery or batteries. The battery or batteries are charged by current pulses and discharge through the tertiary winding to repolarize the diode (and capacitor if present). The secondary winding is poled, with respect to the tertiary winding so that the blocking oscillator is driven by energy from the battery or batteries. The battery charger can operate over a wide range of input voltages with high efficiency, making it useful worldwide. The charger is effective to charge batteries and series connections thereof over a wide range of battery voltages. The charger will only function if at least one rechargeable battery is in circuit for charging. The charger may include circuitry for automatically taking substantially charged batteries or battery out of the charge path.

Universal battery charger

A method and apparatus for regulating a voltage controlled amplifier to operate within Class A and Class AB extremes generate a bias control signal from one or more signals in a system including the voltage controlled amplifier and applying the bias control signal to the voltage controlled amplifier to affect operation within the extremes.

Dynamically biased voltage controlled element

A monolithically fabricated voltage controlled element includes first and second pairs of transistors where bases of two of the transistors are connected to a reference voltage and bases of the remaining two transistors are connected to a control signal, emitters of transistors of respective pairs are connected together, where differences in collector currents between transistors of said pairs define output signals from said element, and includes circuitry providing variable compensation, user-selectable class A or class AB operation and distortion correction.

Monolithic voltage controlled element

A programmable adjustable distortion amplifier circuit has a first channel having an adjustable gain and a filter for filtering high and low frequency components of signal processed by the first channel, a second channel having an adjustable gain and a filter for filtering high and low frequency components of signal processed by the second channel, a parametric equalizer providing adjustable preselectable frequency bandwidth and a vacuum tube amplifier and support circuitry permitting adjustment of distortion of signal processed by the second channel by a preselected amount. An optional phase shift circuit delays a portion of signal processed by the second channel with the delayed portion provided to the second channel downstream of the parametric equalizer but upstream of the tube. A summing device combines output signals of the first and second channels for input to an adjustable gain control for subsequent input to audio speakers. Switches produce input signals for adjustably preselecting bandwidth of the parametric equalizer, amplitude of the parametric equalizer output and distortion introduced by the tube and support circuitry. A memory stores a plurality of input signals received from the switches and allows selection among the plurality of stored signals for input to the parametric equalizer and to the tube. These input signals control bandwidth of signal having amplitude controlled by the parametric equalizer, amplitude of the parametric equalizer output and the amount of distortion introduced by the tube. The individual circuit components may stand alone and function independently of one another.

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Bethlehem, PA, United States of America

Douglas R Frey