International Business Machines Corporation

Other

Douglas R Chisholm

Richard Allen Kelley

Andrew Boyce McNeill, Jr

John David Wilson

Donall G Bourke

Gary B Hoch

Hartmut R Schwermer

Timothy Vincent Lee

Charles B Perkins, Jr

Carl A Malmquist

Richard L Place

John M Nelson

Roy Y Liu

Gregory D Float

Ed Wachtel

Dean Alan Kalman

Andrew B McNeill

Ernest Nelson Mandese

Wan Lin Leung

Jerry D Dixon

Richard N Mendelson

Robert Dean Yoder

Russell S Padgett

James T Moyer

Francis M Bonevento

Hobart L Kurtz, Jr

Serafin J Garcia, Jr

Mark C Snedaker

Dhruvkumar M Desai

Robert G Iseminger

Sammy D Dodds

Lewis W Brown

A novel PHY concentrator design is disclosed. The PHY concentrator provides switchable dual paths to disk drives from dual controllers. The concentrator uses a common input that is shifted into an internal shift register during the bus reset state and uses an individual TpBias source for each TPA port connection, instead of a common one for all ports. An external shift register can be loaded with an odd/even pattern or a half-on/half-off pattern, which controls the individual TpBias source for each TPA port. The concentrator prevents closed loop conditions from occurring when a pair of concentrators are used to build an array of devices, such as a RAID structure.

Acyclic cable bus having redundant path access

An information handling system transfers command blocks between a host processing side having a host processing unit and a host memory and a local processing side having a local processing unit and a local memory. The command blocks are transferred from the host processing side to the local processing side by storing the host address of the command block in a local side register set. Upon storing the host address a transfer signal is given to a command block transfer controller to start a command block transfer without the local processor unit intervention.

Information handling system for transfer of command blocks to a local

An information handling system transfers command blocks between a host processing side having a host processing unit and a host memory, and a local processing side having a local processing unit and a local memory. The local memory includes a command address queue portion for queuing local command address images containing the local addresses of the command blocks. A command block transfer controller is responsive to the local command address images for storing the transferred command block into a corresponding portion of the local memory.

Information handling system having a local address queue for local

An information handling system transfers data blocks between a host processing side having a host processing unit and a host memory and a local processing side having a local processing unit and a local memory. The host memory includes a status queue memory portion having a plurality of status queue images each image storing a status information relating to a corresponding data transfer. The status information relating to data block transfers are posted on the host processing side. The host processing unit, upon system initialization, sets up a status queue register set within the local processing side defining status queue parameters including the location of the status queue memory portion within the host memory and pointer values pointing to where status queue images are to be stored and from where they are to be retrieved.

Status handling for transfer of data blocks between a local side and a

An information handling system transfers data blocks between a host processing side having a CPU and a host memory and a local processing side having a local processing unit and a local memory. The local memory includes a DCB queue memory portion having a plurality of DCB images each image defining host and local addresses of a corresponding data transfer. The DCB images also store a default status condition representing the most likely condition of a data transfer which in the preferred embodiment is a no error condition. A data transfer status detector determines whether the default status condition is true or false. If true, the default status information relating to a corresponding data block transfer is posted on the host processing side without local processing unit intervention.

Information handling system using default status conditions for transfer

In a data processing system, an input output bus unit (IOBU) is connected to one end of an input output interface controller (IOIC) via an asynchronous bus. The other end of the IOIC is connected to a storage controller (SC) and an input output interface unit (IOIU) via a synchronous bus. The SC and IOIU are connected to a memory unit and an instruction processing unit. The asynchronous bus, which is comprised of three sub-buses and a control bus, conducts signals between the IOIC and an IOBU in an asynchronous 'handshaking' manner. The synchronous bus, which is comprised of two sub-buses and a control bus, conducts signals between the IOIC and the SC/IOIU in an synchronous manner. The IOIC, interconnected between the synchronous bus and asynchronous bus, functions as a buffer between the faster synchronous bus and the slower asynchronous bus. Various operations are performed between an IOBU and the memory unit via the asynchronous bus, IOIC, synchronous bus, and SC/IOIU, such as a unit operation, a storage operation, and a message acceptance operation.

Coupled synchronous-asychronous bus structure for transferring data

Method for performing inter-unit data transfer operations among a

In a data processing system, an input output bus unit (IOBU) is connected one end of an input output interface controller (IOIC) via an asynchronous bus. The other end of the IOIC is connected to a storage controller (SC) and an input output interface unit (IOIU) via a synchronous bus. The SC and IOIU are connected to a memory unit and an instruction processing unit. The asynchronous bus, which is comprised of three sub-buses and a control bus, conducts signals between the IOIC and an IOBU in an asynchronous handshaking manner. The synchronous bus, which is comprised of two sub-buses and a control bus, conducts signals between the IOIC and the SC/IOIU in an synchronous manner. The IOIC, interconnected between the synchronous bus and asynchronous bus, functions as a buffer between the faster synchronous bus and the slower asynchronous bus. Various operations are performed between an IOBU and the memory unit via the asynchronous bus, IOIC, synchronous bus, message acceptance operation.

Method for transferring information between main store and input output

Input output interface controller connecting a synchronous bus to an

A command interface includes ports for transferring information between a host processor and at least one intelligent subsystem which may have attached devices. A Command Interface port receives either a direct command or an indirect command from the host processor, which commands are indicative of a type of operation to be performed by the one subsystem or an attached device. An Attention port receives a code from the host processor which is indicative of which one of the direct command or the indirect command is received at the Command Interface port, and which is also indicative of which of the one intelligent subsystem or a device is to execute the command. A command busy/status port receives a code from the one intelligent subsystem which is indicative of whether or not the Command Interface port and the Attention port are busy, and whether or not the one intelligent subsystem is accepting or rejecting commands. The host processor can read this port without altering or updating the code.

Command delivery for a computing system for transfers between a host and

A plurality of specialized controllers (e.g., 202, 204 & 206), each one adapted to control a particular type of data transfer operation, control the flow of data between a system bus (104) and a local bus (106) on a computer adapter card (102). When the Direct Memory Access (DMA) controller (202) is controlling a DMA operation on the local bus, certain other controllers (204 & 206) can break-in to the current DMA operation, temporarily halting the DMA opertion until the other controller has completed its data transfer operation. To break-in to a DMA operation, handshaking signals between the DMA controller and the local bus interface circuit (212) are temporarily blocked by blocking signals from a break-in logic circuit (210). The break-in circuit includes a four-state state machine to block the handshaking signals at the appropriate times, and to signal the interrupting controller to begin its data transfer operation. When breaking-in to a DMA operation in this manner, the operation of the DMA controller is not altered; instead, to the DMA controller, it appears that the local bus interface circuit is merely slow to respond with its acknowledge handshake.

Bus master interface circuit with transparent preemption of a data

In a data processing system having a system bus for coupling I/O units to a system storage unit, there is provided a mechanism for supplying to the I/O units a line size signal representing the line size of the system storage unit. A further mechanism is located in at least one of the I/O units for responding to this line size signal for adjusting the data transfer size of the I/O unit to match the system storage unit line size.

Data-processing system having a packet transfer type input/output system

In a computer system, a plurality of input/output processors (IOP's) are connected via an asynchronous input/output bus, called an 'SPD' bus, to one side of an input/output interface controller (IOIC). The other side of the IOIC is connected to a storage controller (SC) via a synchronous bus called an 'adapter' bus. The SC is connected to a common system memory and possibly also to an instruction processing unit. The IOIC comprises at least one shared DMA facility for executing DMA read/write storage operations requested by the IOP's via the SPD bus. Each shared DMA facility includes a buffer for holding control information and data to be transmitted between the SC and one of the IOP's. This enables the SPD bus to be released for utilization by otehr IOP's connected thereto during periods of 'storage latency' that occur after a DMA storage operation has been initiated by one IOP.

Method and apparatus for increasing system throughput via an

A peripheral device address assignment mechanism is described which does not require the use of plugboards or jumpers. This mechanism enables a host processor to select any desired peripheral device and set its device address to any desired value at any desired time. This is accomplished by providing each peripheral device control unit with a loadable device address register for holding the device address assigned to its peripheral device. Each device control unit is further provided with circuitry responsive to the appearance of a unique I/O command on the processor I/O bus and to the activation of a unique set of the I/O bus data lines by the processor for loading into its device address register the desired device address value as supplied thereto by the processor via the I/O bus.

Dynamic device address assignment mechanism for a data processing system

A data processor input/output controller which is particularly useful as a microcontroller for the transfer of data between a host processor and one or more peripheral input/output devices in a digital data processing system. This input/output (I/O) controller is a subchannel controller for offloading a goodly portion of the subchannel control function from the host processor. This I/O controller includes a microprocessor for assisting and supervising the controller internal operations. Also included in the controller is an automatic high-speed data bypass mechanism whereby data may be transferred from the host processor to the I/O device or vice versa without having to pass through the microprocessor and without requiring any intervention on the part of the microprocessor during such automatic transfer. Provision is made for enabling the microprocessor to perform other functions, such as the presentation of interrupts to the host processor and the servicing of additional I/O commands from the host processor concurrently with the transfer of data via the automatic bypass mechanism. This capability is particularly useful where two or more I/O devices are connected to the controller. The automatic bypass mechanism is constructed to communicate with the host processor in a cycle steal mode. A look-ahead mechanism is provided for more quickly issuing the cycle steal requests to the host processor when operating in the automatic bypass mode.

Growing community of inventors

Delray Beach, FL, United States of America

Douglas R Chisholm