Micrel, Incorporated

Douglas Paul Anderson

William Andrew Burkland

Peter Chambers

Joseph James Judkins

An accelerator circuit is incorporated in a laser diode system for accelerating the turn-on operation of the laser diode independent of the control loop bandwidth of the laser diode system. The accelerator circuit provides a boost current to a compensation capacitor upon laser turn-on which compensation capacitor operates to establish the control loop bandwidth of the laser diode system. The boost current enables the control loop to increase the bias current to the laser diode quickly. When the laser diode reaches the desired operating point, the boost current is terminated and the control loop of the laser diode system resumes normal control of the bias current. In one embodiment, the accelerator circuit includes a timer circuit controlling a current source to implement open loop turn-on control. In another embodiment, the accelerator circuit includes a comparator circuit working in conjunction with an one-shot logic circuit for providing close loop control.

Laser turn-on accelerator independent of bias control loop bandwidth

A power budget monitoring circuit in a multi-port PSE includes a differential amplifier and a transistor for setting a reference voltage across a first resistor to establish a reference current, multiple current mirror output devices each associated with a power port of the PSE, a second resistor and a comparator. Each current mirror output device provides an output current indicative of the power demanded by the associated power port where the output currents are summed at a second node into a monitor current. The second resistor has a resistance value proportional to a maximum power budget of the PSE and receives the monitor current. A monitor voltage develops across the second resistor indicative of the total power demanded by the power ports. The comparator compares the monitor voltage to the reference voltage and provides a comparator output signal indicating whether the maximum power budget of the PSE has been exceeded.

Power budget management in power over ethernet systems

An AC maintain power signature detection circuit in a power sourcing equipment (PSE) for a Power over Ethernet system injects an AC test signal onto a power port of the PSE. The AC test signal is driven onto a first power terminal of the power port through a sense resistor. The voltages across the sense resistor are measured and scaled by first and second resistor dividers having different resistor ratios. The voltage and the scaled voltage at the first power terminal side of the sense resistor have a peak voltage being proportional to the load impedance of the load coupled to the power port. The comparator compares the scaled voltages measured across the sense resistor and generates the output signal indicative of the load impedance at the power port.

Detection of presence or absence of AC maintain power signature in power-over-ethernet system

A BiCMOS auxiliary output driver is provided to maintain output logic signal levels when integrated circuit chip power supply voltage is outside its nominal range. When the power supply voltage level is within design tolerance for a MOSFET output driver stage, the auxiliary output driver is off; when below design tolerance, the auxiliary output driver is turned on. Driver stage output pad signal level is maintained at a desired state level by the auxiliary output driver whenever the power supply slips below its design tolerance range.

Auxiliary output driver

A voltage-controlled variable duty-cycle oscillator includes a current generator whose current Iref mirrored in three one-shots that each include two pair of series-coupled MOS transistors and a timing capacitor. The timing capacitor is precharged to Vcc in the first two one-shots, and to a lesser voltage Vcon in the third one-shot. The oscillator also includes pre and a post-NOR-gate logic. Output signals from the two one-shots are coupled to the pre NOR-gate logic to generate an intermediate oscillator signal whose duty cycle is determined by Iref and by the first two timing capacitors. The intermediate oscillator signal and output from the third one-shot are combined in the post NOR-gate logic to yield a VCO output signal whose duty cycle is determined by the ratio of the timing capacitor in the third one-shot compared to the sum of the timing capacitors in the first and second one-shots. VCO output signal duty cycle is a fairly linear function of Vcon.

Growing community of inventors

Nevada, IA, United States of America

Douglas Paul Anderson