Xilinx, Inc.

Douglas P Wieland

Chih-Tsung Huang

Charles R Erickson

Kerry M Pierce

Sankaranarayanan Srinivasan

Sandor S Kalman

W Story Leavesley, Iii

Emil S Ochotta

George L McHugh

Method and apparatus for implementing a pre-implemented circuit design for a programmable logic device is described. In one example, a definition of the pre-implemented circuit design is obtained (). The definition includes a first physical implementation and a first logical implementation. A second logical implementation is produced () for an instance of the pre-implemented circuit design using the first logical implementation. A second physical implementation is produced () for then instance of the pre-implemented circuit design using the first physical implementation.

Method and apparatus for implementing a pre-implemented circuit design for a programmable logic device

A direct connect mesh routing structure is provided for interconnecting configurable logic blocks within a programmable logic device. The structure includes multi-bit interconnect busses and a highly regular structure distributed throughout a configurable array enabling high direct interconnect utilization to adjacent and non-adjacent logic blocks, high speed circuit implementation, and improved timing characteristics. The direct connections of the invention are the preferred interconnect path between logic blocks because they substantially reduce the average interconnect delay, thereby allowing the programmable logic device to operate at a higher speed.

Routing architecture using a direct connect routing mesh

An FPGA architecture is provided which uses logic unit output lines of more than one length and provides extension lines to increase the reach of a logic unit output line. The architecture allows extremely fast connections between one logic unit and another. Also, all logic unit output lines drive about the same number of buffered programmable interconnection points (PIPs) so that the signal delay between one logic unit and the next can be predicted regardless of the functions and routing which have been selected by a user. The frequency of PIPs decreases as distance from the originating logic unit increases. This has the benefit of cooperating with software which tends to place interconnected logic in close proximity. The architecture is preferably implemented with a tile layout with one logic unit in each tile, and logic unit input and output lines extending through several tiles. Thus one tile boundary is like another and there is minimum hierarchy.

Interconnect architecture for field programmable gate array using

Interconnect architecture for field programmable gate array

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Sunnyvale, CA, United States of America

Douglas P Wieland