Freescale Semiconductor,inc.

Nxp Usa, Inc.

Motorola Corporation

The Penn State Research Foundation

Nxp B.v.

Douglas Michael Reber

Mehul D Shroff

Edward Outlaw Travis, Jr

Sergio A Ajuria

Phuc M Nguyen

Stephen J Fonash

Ertugrul Demircan

Lawrence N Herr

Stephen R Crown

Xin Lin

Suresh Venkatesan

Olubunmi O Adetutu

Alexander Barr

Michael A Stockinger

Stuart E Greer

Ramnath Venkatraman

Brian George Anthony

David Clegg

Rishi Bhooshan

Dwarka Prasad

Gregor Braeckelmann

Donald E Smeltzer

Rebecca G Cole

Kenneth J Danti

Inder Mohan Bhawnani

Phuc M Nyugen

Wafer processing techniques, or methods for forming semiconductor rides, are disclosed for fabricating plated pillar dies having die-level electromagnetic interference (EMI) shield layers. In embodiments, the method includes depositing a metallic seed layer over a semiconductor wafer and contacting die pads thereon. An electroplating process is then performed to compile plated pillars on the metallic seed layer and across the semiconductor wafer. Following electroplating, selected regions of the metallic seed layer are removed to produce electrical isolation gaps around a first pillar type, while leaving intact portions of the metallic seed layer to yield a wafer-level EMI shield layer. The semiconductor wafer is separated into singulated plated pillar dies, each including a die-level EMI shield layer and plated pillars of the first pillar type electrically isolated from the EMI shield layer.

Plated pillar dies having integrated electromagnetic shield layers

Embodiments are disclosed for semiconductor manufacturing using disposable test circuitry formed within scribe lanes. The manufacturing steps can include forming device circuitry within a semiconductor die and forming test circuitry within a scribe lane. One or more electrical connection route lines are also formed that connect the device circuitry and test circuitry blocks. Further, each die can be connected to a single test circuitry block, or multiple dice can share common test circuitry blocks. After testing, the electrical connection route line(s) are sealed, and the test circuitry is discarded when the device dice are singulated. For certain embodiments, the edge of the devices dice are encapsulated with a protective metal layer, and certain other embodiments include protective sealrings through which the connection route lines pass to enter the dice from the test circuitry blocks within the scribe lanes.

Semiconductor manufacturing using disposable test circuitry within scribe lanes

A semiconductor package with an embedded capacitor and corresponding manufacturing methods are described. The semiconductor package with the embedded capacitor includes a semiconductor die having a first metal layer extending across at least a portion of a first side of the semiconductor die and a package structure formed on the first side of the semiconductor die. A first electrical conductor of the embedded capacitor is formed in the first metal layer of the semiconductor die. The package structure includes a second metal layer that has formed therein a second electrical conductor of the embedded capacitor. A dielectric of the embedded capacitor is positioned within either the semiconductor die or the package structure of the semiconductor package to isolate the first electrical conductor from the second electrical conductor of the embedded capacitor.

Semiconductor package with embedded capacitor and methods of manufacturing same

A method of making a semiconductor device with an air gap for a terminal of a semiconductor device includes forming a sacrificial sidewall spacer and removing the spacer after the formation of contact structures for the semiconductor device. The air gap is located in portions of the wafer where the sacrificial air gap was removed. Since the contacts are formed prior to the removal of the sacrificial spacers, air gaps can advantageously be formed without electrically conductive contact material undesirably being deposited in locations of the desired air gap.

Post contact air gap formation

A semiconductor device and a method for making the semiconductor device are provided. The method of making the semiconductor device may include patterning a layer for a first conductor and a second conductor, plating patterned portions of the layer to form the first conductor and the second conductor, removing patterned material to form an air gap between the first conductor and the second conductor, applying a self-supporting film on top of the first conductor and the second conductor to enclose the air gap, and reacting the self-supporting film causing the self-supporting film to be substantially non-conductive.

Method of forming inter-level dielectric structures on semiconductor devices

A method for forming a semiconductor structure includes forming a first metal layer over a first dielectric layer, forming a first graphene layer on at least one major surface of the first metal layer, and forming a second dielectric layer over the first metal layer and the first graphene layer. The method further includes forming an opening in the second dielectric layer which exposes the first metal layer, forming a second metal layer over the second dielectric layer and within the opening, and forming a second graphene layer on at least one major surface of the second metal layer, wherein the second graphene layer is also formed within the opening.

Semiconductor device with graphene encapsulated metal and method therefor

A multigate transistor is formed on a wafer with a first material and a second material. Portions of the second material are selectively removed from the first material to form an opening in the first material. An epitaxially grown semiconductor material is grown from a seed layer into the opening. A portion of the first material is removed around the epitaxially grown semiconductor material in the opening and a gate material is formed in locations of the removed first material. The epitaxially grown semiconductor material in the opening serves as a channel region for a multigate transistor and the gate material serves as a gate for the multigate transistor.

Multigate transistor

In some embodiments, a substrate contact is formed by forming a first gate structure and a second gate structure. The first gate structure is formed in a first volume in a first area of the wafer and the second gate structure is formed in a second volume in a second area of the wafer. The gate dielectric is removed from the wafer in a first area of the wafer but remains in the second area. A first sidewall spacer formed for the gate structure and a second sidewall spacer is formed for the second gate structure. In some embodiments, the first gate structure can be utilized as a substrate contact and the second gate structure can be utilized as a gate of a transistor. In other embodiments, the first gate structure and the second gate structure can be removed and a metal gate material can be deposited in opening for forming a substrate contact and a metal gate, respectively. In some embodiments, the first gate structure (or the replacement metal gate structure) can be used as part of a body contact to bias the body of a transistor. In other embodiments, the first gate structure (or replacement metal gate structure) can be used as part of a current terminal contact for the transistor.

Substrate contacts for a transistor

An integrated circuit device includes a first line in a first metal layer of the integrated circuit device, wherein the first line forms at least a portion of an interconnect, a second line in a second metal layer of the integrated circuit device, and a first via that couples the first line to the second line. The integrated circuit device further includes a first stressor disposed at a first area of the interconnect, wherein the first area at least partially overlaps the first via, wherein the first stressor alters an electromigration stress profile for the interconnect by altering a stress at the first area to be less tensile.

Apparatus and method for placing stressors within an integrated circuit device to manage electromigration failures

A semiconductor device includes a circuitry die and a solar cell die. The circuitry die includes a plurality of interconnect layers on a front side of the circuitry die, a metallization layer on a back side of the circuitry die, and at least one TSV (through substrate via) that makes an electrical connection between a last metal interconnect layer on the front side of the circuitry die and the metallization layer on the back side of the circuitry die. The solar cell die is configured to power the circuitry die. The solar cell die includes a transparent contact on a front side of the solar cell die. A back side of the solar cell die is attached to the back side of the circuitry die and makes electrical contact with the metallization layer on the back side of the circuitry die.

Solar cell powered integrated circuit device and method therefor

A method for design rule verification is provided. The method comprises: providing a design rule check (DRC) deck based on a design rule manual (DRM) having a plurality of design rules; providing a plurality of primitive objects; creating a plurality of collection objects, each collection object using one or more primitive objects; using the plurality of collection objects, creating a plurality of DRM test cases; assigning names to each of the plurality of DRM test cases, each of the names based on a rule name of the plurality of design rules and on an expected pass or fail indication; and using the plurality of named DRM test cases to verify the DRC deck.

Method for verifying design rule checks

A semiconductor structure comprising a fuse/resistor structure over a functional layer having a substrate. The fuse/resistor structure includes a via, a first interconnect layer, and a second interconnect layer. The via is over the functional layer and has a first end and a second end vertically opposite the first end, wherein the first end is bounded by a first edge and a second edge opposite the first edge and the second end is bounded by a third edge and a fourth edge opposite the third edge. The first interconnect layer includes a first metal layer running horizontally and contacting the first end and completely extending from the first edge to the second edge. The second interconnect layer includes a second metal layer running horizontally and contacting the second end of the via and extending past the third edge but reaching less than half way to the fourth edge.

Fuse/resistor utilizing interconnect and vias and method of making

This disclosure describes an approach to create a library of pre-marked circuit element objects and use the pre-marked circuit element object library to design and fabricate an integrated circuit. Each of the circuit element objects are 'pre-marked' and include embedded voltage markers having independent pre-assigned voltage values for each terminal in the circuit element object. When a circuit designer inserts a pre-marked circuit element object in a schematic design, the design tool determines whether each of the circuit element object terminal's pre-assigned voltage values match their corresponding nets to which they are connected. When the circuit designer completes the schematic design that includes valid nets throughout the schematic design, the design tool generates a layout design from the schematic design. The design tool, in turn, generates mask layer data from the layout design when the layout design passes verification testing.

Growing community of inventors

Austin, TX, United States of America

Douglas Michael Reber