Irvine Sensors Corporation

Other

Aprolase Development Co., LLC

Douglas Marice Albert

Keith D Gann

Volkan H Ozguz

W Eric Boyd

James S Yamaguchi

Angel Antonio Pepe

Andrew N Camien

Prepackaged chips, such a memory chips, are vertically stacked and bonded together with their terminals aligned. The exterior lead frames are removed including that portion which extends into the packaging. The bonding wires are now exposed on the collective lateral surface of the stack. In those areas where no bonding wire was connected to the lead frame, a bare insulative surface is left. A contact layer is disposed on top of the stack and vertical metalizations defined on the stack to connect the ends of the wires to the contact layer and hence to contact pads on the top surface of the contact layer. The vertical metalizations are arranged and configured to connect all commonly shared terminals of the chips, while the control and data input/output signals of each chip are separately connected to metalizations, which are disposed in part on the bare insulative surface.

Vertically stacked pre-packaged integrated circuit chips

A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations on each die on the wafer at the reticle level using a series of semiconductor processing steps. The wafer is passivated and the vias are filled with a conductive material. The bond pads on the die are exposed and a metallization reroute from the user-selected bond pads and vias is applied. The wafer is then segmented to form thin, stackable layers that can be stacked and vertically electrically interconnected using the conductive vias, forming high-density electronic modules which may, in turn, be further stacked and interconnected to form larger more complex stacks.

Stackable semiconductor chip layer comprising prefabricated trench interconnect vias

A method for electrical interconnection of angularly disposed and abutted conductive patterns is disclosed along with a device created from the method. Conventional wire bonding equipment is used to apply a conductive metal ball at the junction of angularly disposed conductive patterns by orienting a cornerbond assembly whereby one or more conductive metal balls are orthogonally applied and electrically connected to the respective conductive patterns.

Method for electrical interconnection of angularly disposed conductive patterns

Prepackaged chips, such a memory chips, are vertically stacked and bonded together with their terminals aligned. The exterior lead frames are removed including that portion which extends into the packaging. The bonding wires are now exposed on the collective lateral surface of the stack. In those areas where no bonding wire was connected to the lead frame, a bare insulative surface is left. A contact layer is disposed on top of the stack and vertical metallizations defined on the stack to connect the ends of the wires to the contact layer and hence to contact pads on the top surface of the contact layer. The vertical metallizations are arranged and configured to connect all commonly shared terminals of the chips, while the control and data input/output signals of each chip are separately connected to metallizations, which are disposed in part on the bare insulative surface.

Method and apparatus for connecting vertically stacked integrated circuit chips

A stackable microcircuit layer formed from a plastic encapsulated microcircuit (PEM) and method of making the same is disclosed. The method involves the steps of starting with a commercially available PEM (e.g. a plastic Thin Small Outline Package or TSOP) that contains a microcircuit or die within an encapsulant and modifying the PEM to expose conductive members that are electrically connected to the microcircuit's bond pads. In the case of a TSOP, the preferred modifying step is accomplished by top grinding the TSOP in order to remove the lead frame that was secured above the die and encapsulated along with it in the TSOP. Next, reroute metallization is applied in order to connect the conductive members that were exposed by the top grinding, to an edge of the modified PEM. Finally, if appropriate, the modified PEM is thinned through backside grinding and diced to a desired area, in order to provide a stackable microcircuit layer that may form a part of a dense electronic package. The PEM may be of any suitable type and the stackable microcircuit layers that results from application of this invention may be stacked as provided or included in &ldquo;neo-chips&rdquo; that are of greater area, that include additional die, or both. The stackable microcircuit layers made according to this invention beneficially use PEMs that are readily available and that include die that were typically &ldquo;burned in&rdquo; by the manufacturer rather than merely tested on a statistical basis as is usually the case with bare die.

Stackable microcircuit layer formed from a plastic encapsulated microcircuit

A system calibrates a user's brain region (e.g., the primary visual cortex or V region) to actual sensory information (e.g., the visual field), and enables imagined sensory information (e.g.; dynamic mental imagery) to be interpreted as computer input. The system includes a configuration engine and an input device control engine. The configuration engine includes a test pattern; a functional information gatherer for presenting the test pattern to a user; a brain-scanning device interface for obtaining functional information from a region in the user's brain that provides a physiological response to the test pattern and that receives feedback corresponding to imagined sensory information; and a mapping engine for using the functional information to map the user's brain region to the test pattern. The input device control engine includes a brain-scanning device interface for obtaining functional information from a brain region that provides a physiological response to actual sensory information and that receives feedback corresponding to imagined sensory information; an interpretation engine for interpreting the feedback; and a computer control engine for using the interpreted feedback as computer input.

Growing community of inventors

Yorba Linda, CA, United States of America

Douglas Marice Albert