Sun Microsystems, Inc.

Douglas M Priest

J Arjun Prabhu

Michael J Parks

A method, apparatus, and computer program product for handling IEEE 754 standard exceptions for Single Instruction Multiple Data (SIMD) instructions. Each SIMD sub-operation's corresponding IEEE 754 exception flag is bit-wise &ldquo;ORed&rdquo; with an accrued exception field if a trap enable mask field is configured to mask the exception, with the &ldquo;ORed&rdquo; result written back in the accrued exception field. If the trap enable mask field is configured to enable the exception, the accrued exception field and a current exception field are cleared, and an unfinished floating-point exception flag is set in a floating-point trap type field. The actual sub-operation(s) causing the exception is determined through software.

Exception handling for SIMD floating point-instructions using a floating point status register to report exceptions

In a computer system, a method and system for verifying whether a floating-point logic unit correctly directly rounds floating-point numbers when conducting multiplication, square root, and division operations. A bit sequence that represents a directed boundary condition for a mathematical operation is identified. This sequence is then recast in terms of a series of integer equations. A recurrence is used to solve these equations to produce difficult test data. When solving the equations, any intermediate terms that exceed the computer's precision are discarded. The logic then conducts the mathematical operation under inspection using the test cases. The logic's computed value is then compared to an expected value. If the computed value equals the expected value, the logic has accurately performed the operation. If not, the logic is faulty.

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Douglas M Priest