Intel Corporation

Ross Technology Corporation

Douglas M Carmean

Eric A Sprangle

Per H Hammarlund

David J Sager

Muntaquim F Chowdhury

Stephen H Gunther

Edward Allyn Burton

Robert Dale Cavin

John H Crawford

Herbert H Hum

Linda J Rankin

Rajesh Kumar

Frank Binns

Jack D Pippin

John M Bauer

Brent E Lince

Francis X Mckeen

Darrell D Boggs

Ronak Singhal

Michael D Upton

Anwar Q Rohillah

Rohit A Vidwans

Karol F Menezes

Thomas F Toll

Yung-Hsiang Lee

Jason W Brandt

Hong Wang

Edward Thomas Grochowski

Baiju V Patel

Stephan Jourdan

Scott Dion Rodgers

Prashant Sethi

Robert J Greiner

Thomas D Fletcher

Gautham N Chinya

John Thomas Shen

Keng L Wong

Shivnandan D Kaushik

Bryant E Bigbee

Xiang Chris Zou

Richard A Hankins

Andrew Thomas Forsyth

James Paul Held

Alexandre J Farcy

Robert F Krick

Javed Sabir Barkatullah

Keshavan K Tiruvallur

Ramacharan Sundararaman

Sanjiv M Shah

John L Reid

Ryan N Rakvic

James Charles Abel

Paul Albert Lalonde

Zhongying Zhang

David K Poulsen

Madhavan Parthasarathy

Roshan J Fernando

Morris Marden

Robert L Hinton

John Cruz Mejia

Yatin G Mundkur

Pierre Michaud

Harish Kumar

Kathakali Debnath

Dave L Hill

Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.

Distribution of tasks among asymmetric processing elements

Techniques are disclosed to control power and processing among a plurality of asymmetric cores. In one embodiment, a multi-core processor includes first and second processing cores, each including an arithmetic logic unit and an instruction decoder, wherein the first processing core is capable of operating at a higher processing throughput than the second processing core, wherein the first and second processing cores have different instruction sets, wherein, in response to an occurrence of an event, a task processed on the first processing core is to be translated and transferred to the second processing core after saving a core state of the first processing core and providing the core state to the second processing core, wherein instructions to run on the second processing core are translated to the instruction set of the second processing core by a software binary translation shell, and wherein the first and second processing cores are to concurrently execute instructions according to their own instruction sets.

A computer processor includes a decoder for decoding machine instructions and an execution unit for executing those instructions. The decoder and the execution unit are capable of decoding and executing vector instructions that include one or more format conversion indicators. For instance, the processor may be capable of executing a vector-load-convert-and-write (VLoadConWr) instruction that provides for loading data from memory to a vector register. The VLoadConWr instruction may include a format conversion indicator to indicate that the data from memory should be converted from a first format to a second format before the data is loaded into the vector register. Other embodiments are described and claimed.

Methods, apparatus, and instructions for converting vector data

Methods and systems may involve determining a user attention level based on video stream data associated with a first participant in an always-on video conferencing session. The video stream data may be modified based on the user attention level to obtain modified video stream data that is automatically adjusted for privacy. In addition, the modified video stream data may be transmitted to one or more other participants in the video conferencing session.

Automated privacy adjustments to video conferencing streams

In an embodiment, a processor includes a decode logic to receive and decode a first memory access instruction to store data in a cache memory with a replacement state indicator of a first level, and to send the decoded first memory access instruction to a control logic. In turn, the control logic is to store the data in a first way of a first set of the cache memory and to store the replacement state indicator of the first level in a metadata field of the first way responsive to the decoded first memory access instruction. Other embodiments are described and claimed.

Providing extended cache replacement state information

Replay instruction morphing. One disclosed apparatus includes an execution unit to execute an instruction. A replay system replays an altered instruction if the execution unit executes the instruction erroneously.

Replay instruction morphing

Systems and methods of managing threads provide for supporting a plurality of logical threads with a plurality of simultaneous physical threads in which the number of logical threads may be greater than or less than the number of physical threads. In one approach, each of the plurality of logical threads is maintained in one of a wait state, an active state, a drain state, and a stall state. A state machine and hardware sequencer can be used to transition the logical threads between states based on triggering events and whether or not an interruptible point has been encountered in the logical threads. The logical threads are scheduled on the physical threads to meet, for example, priority, performance or fairness goals. It is also possible to specify the resources that are available to each logical thread in order to meet these and other, goals. In one example, a single logical thread can speculatively use more than one physical thread, pending a selection of which physical thread should be committed.

Decoupling the number of logical threads from the number of simultaneous physical threads in a processor

Disclosed are embodiments of a system, methods and mechanism for management and translation of mapping between logical sequencer addresses and physical or logical sequencers in a multi-sequencer multithreading system. A mapping manager may manage assignment and mapping of logical sequencer addresses or pages to actual sequencers or frames of the system. Rationing logic associated with the mapping manager may take into account sequencer attributes when such mapping is performed Relocation logic associated with the mapping manager may manage spill and fill of context information to/from a backing store when re-mapping actual sequencers. Sequencers may be allocated singly, or may be allocated as part of partitioned blocks. The mapping manager may also include translation logic that provides an identifier for the mapped sequencer each time a logical sequencer address is used in a user program. Other embodiments are also described and claimed.

Sequencer address management

An integrated, on-chip thermal management system providing closed-loop temperature control of an IC device and methods of performing thermal management of an IC device. The thermal management system comprises a temperature detection element, a power modulation element, a control element, and a visibility element. The temperature detection element includes a temperature sensor for detecting die temperature. The power modulation element may reduce the power consumption of an IC device by directly lowering the power consumption of the IC device, by limiting the speed at which the IC device executes instructions, by limiting the number of instructions executed by the IC device, or by a combination of these techniques. The control element allows for control over the behavior of the thermal management system, and the visibility element allows external devices to monitor the status of the thermal management system.

Methods and apparatus for thermal management of an integrated circuit die

A computer processor includes a replay system to replay instructions which have not executed properly and a first event pipeline coupled to the replay system to process instructions including any replayed instructions. A second event pipeline is provided to perform additional processing on an instruction. The second event pipeline has an ability to detect one or more faults occurring therein. The processor also includes a synchronization circuit coupled between the first event pipeline and the second event pipeline to synchronize faults occurring in the second event pipeline to matching instruction entries in the first event pipeline.

Technique for synchronizing faults in a processor having a replay system

Breaking replay dependency loops in a processor using a rescheduled replay queue. The processor comprises a replay queue to receive a plurality of instructions, and an execution unit to execute the plurality of instructions. A scheduler is coupled between the replay queue and the execution unit. The scheduler speculatively schedules instructions for execution and increments a counter for each of the plurality of instructions to reflect the number of times each of the plurality of instructions has been executed. The scheduler also dispatches each instruction to the execution unit either when the counter does not exceed a maximum number of replays or, if the counter exceeds the maximum number of replays, when the instruction is safe to execute. A checker is coupled to the execution unit to determine whether each instruction has executed successfully. The checker is also coupled to the replay queue to communicate to the replay queue each instruction that has not executed successfully.

Breaking replay dependency loops in a processor using a rescheduled replay queue

Growing community of inventors

Beaverton, OR, United States of America

Douglas M Carmean