Hughes Aircraft Company

United States of America As Represented by the Secretary of the Air Force

Douglas M Benedict

Lee W Tower

James R Gaskill, Jr

Jeffrey A Wagner

A signal processor architecture that comprises a data network having multiple ports, a control bus, and a plurality of signal processing clusters connected to at least two ports and the control bus. Each signal processing cluster comprises a system control processor connected to the control bus, a second control bus, and a global bulk memory having multiple ports. A plurality of functional processing elements are connected to the system control processor by way of the second control bus, and each are connected to a port of the global bulk memory. The global bulk memory comprises a subdata flow network having multiple gateways and full crossbar interconnectivity between each of the multiple gateways. The data network and subdata flow network allow data to be transferred between functional processing elements in the signal processing cluster and any functional processing element and global bulk memory in another signal processing cluster, and allow data to be transferred from any functional processing element into and out of the processor architecture. The first control bus is arbitrated for access on a message by message basis and the data network is arbitrated on a message by message basis for transfers between ports. This results in a relatively loose coupling between the signal processing clusters. The second control bus is arbitrated for access on a word by word basis and the global bulk memory is arbitrated for port access on each global bulk memory cycle. This results in tight coupling within each signal processing cluster.

Multiple cluster signal processor architecture

A universal timing array (UTA) comprising a branch and increment logic circuit and multiple 2-bit counter cells is fabricated as a single large scale integrated circuit and is adapted to implementing various timing and control functions in digital computers and radar signal processors. Implementation of the UTA functional design using emitter coupled logic circuitry and special circuit design features improves UTA performance by increasing operating clock frequency, widening operating temperature range and reducing on-chip complexity. A specific embodiment utilizes a standard universal digital array chip having specially selected cell placements and interconnecting routing patterns.

Universal timing array

Apparatus is provided comprising a plurality of master latches whose outputs are selectively connected to a single-slave latch. The outputs of the slave latch may be discretionarily connected to particular master latch inputs depending upon the specific circuit arrangement desired. Both the master latches and the slave latch may incorporate implicit input gating which implement particular logic functions.

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Santa Monica, CA, United States of America

Douglas M Benedict