Intel Corporation

Douglas L Gabel

James E Akiyama

Peter D MacWilliams

Kuljit Singh Bains

Jonathan J Huang

Willem M Beltman

Vered Bar Bracha

Orville H Christeson

Binuraj K Ravindran

Sylvia Downing

Sean T Murphy

Ze'ev Rivlin

David J Harriman

Narayan Biswal

James H Ewertz

A system, apparatus, method, and computer program product for a speaking aid. The system including network interface circuitry to receive speech input from a user. The speech input includes a partial sentence with a missing word or the partial sentence with a stuttered word. The system also includes a processor coupled to the network interface circuitry and one or more memory devices coupled to the processor. The one or more memory devices include instructions, that when executed by the processor, cause the system to detect a stutter or pause in the speech input, predict the stuttered word or the missing word, present a predicted word from an n-best list to the user; and if a prompt is received from the user, present a next word from the n-best list until the user speaks a correct word to replace the stutter or the pause.

Time capsule based speaking aid

A system, method, apparatus and computer readable medium for hierarchical speech recognition resolution. The method of hierarchical speech recognition resolution on a platform includes receiving a speech stream from a microphone. The speech stream is resolved using a lowest possible level automatic speech recognition (ASR) engine of multi-level ASR engines. The selection of the lowest possible level ASR engine is based on policies defined for the platform. If resolution of the speech stream is rated less than a predetermined confidence level, the resolution of the speech stream is pushed to a next higher-level ASR engine of the multi-level ASR engines until the resolution of the speech stream meets the predetermined confidence level without violating one or more policies.

Hierarchical speech recognition resolution

In one embodiment of the invention, a memory integrated circuit is provided including an address decoder to selectively access memory cells within a memory array; a mode register with bit storage circuits to store an enable bit and at least one sub-channel select bit; and control logic. The control logic is coupled to a plurality of address signal lines, the address decoder, and the mode register. In response to the enable bit and the at least one sub-channel select bit, the control logic selects one or more of the address signal lines to capture independent address information to support independent sub-channel memory accesses into the memory array. The control logic couples the independent address information into the address decoder.

Memory controller interface for micro-tiled memory access

Embodiments of the invention are generally directed to systems, methods, and apparatuses for encapsulation of high definition audio data over an input/output interconnect. In some embodiments, a system includes tunneling logic coupled with a high definition (HD) audio controller. The tunneling logic may receive digital audio data from the HD audio controller, encapsulate the digital audio data in a message suitable for an in-band input/output (IO) interconnect, and send the message to an add-in graphics card via the in-band input/output IO interconnect. Other embodiments are described and claimed.

Encapsulation of high definition audio data over an input/output interconnect

In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage circuits to store one or more identity bits of an identity value. The control logic provides independent sub-channel memory access into the memory integrated circuit in response to the one or more identity bits stored in the register.

Identifying and accessing individual memory devices in a memory channel

Micro-tile memory interfaces

In one embodiment of the invention, a write cache line with a unique bit pattern is written into memory in a memory channel at a starting address. An attempt is made to enable micro-tile memory accesses into each memory integrated circuit on memory modules in the memory channel. A read cache line is read from memory in the memory channel at the starting address. The bit patterns of the read cache line and the write cache line are compared. If in the comparison it is determined that the bit pattern of the read cache line differs from the write cache line, then micro-tile memory access is enabled into each memory integrated circuit on memory modules in the memory channel. If in the comparison it is determined that the bit pattern of the read cache line is the same as the bit pattern of the write cache line, then micro-tile memory access is not supported and cannot be enabled in each memory integrated circuit on memory modules in the memory channel.

Automatic detection of micro-tile enabled memory

An improved process for updating a nonvolatile memory of a computer system includes selecting a logical area of the nonvolatile memory to update. Protected procedures are copied from one of the selected logical area and an update file. Information from the update file is copied to the nonvolatile memory in accordance with the copied protected procedures. Another method of updating the nonvolatile memory includes selecting at least a portion of the nonvolatile memory to update. Protected procedures including an updated memory map are copied from an update file. Information from the update file is copied to the nonvolatile memory in accordance with the copied protected procedures. An update file to facilitate the improved update processes includes a header section and a update information section. The update information section includes updated code and data for the nonvolatile memory. The header includes a code usage indicator, and offsets to an update table and protected procedures in order to facilitate the update process. The code usage indicator indicates whether the protected procedures are copied from the update file or the nonvolatile memory. The offsets locate the update table and the protected procedures within the update file so that they can be copied to the system memory for use during the update process.

Dynamic nonvolatile memory update in a computer system

A computer system wherein a portion of code/data stored in a non-volatile memory device can be dynamically modified or updated without removing any covers or parts from the computer system. The computer system of the preferred embodiment includes a flash memory component coupled to a computer system bus for storing non-volatile code and data. Using the present invention, the contents of a portion of the flash memory may be replaced, modified, updated, or reprogrammed without the need for removing and/or replacing any computer system hardware components. The flash memory device used in the preferred embodiment contains four separately erasable/programmable non-symmetrical blocks of memory. One of these four blocks may be electronically locked to prevent erasure or modification of its contents once it is installed. This configuration allows the processing logic of the computer system to update or modify any selected block of memory without affecting the contents of other blocks. One memory block contains a normal BIOS. An electronically protected flash memory area is used for storage of a recovery BIOS which is used for recovery operations. The present invention also includes hardware for selecting one of the two available update modes: normal or recovery. Thus, using a mode selection apparatus, either a normal system BIOS or a recovery BIOS may be activated.

Dynamic non-volatile memory update in a computer system

A computer system wherein a paging technique is used to expand the useable non-volatile memory capacity beyond a fixed address space limitation. The computer system of the preferred embodiment includes a flash memory component for storing non-volatile code and data including a system BIOS in the upper 128K of memory. The useful BIOS memory space is effectively increased while maintaining the address boundary of the upper 128K region. The address space of the non-volatile memory device is logically separated into distinct pages of memory (Pages 1-4). Using the apparatus and techniques of the present invention, Page 1, Page 3 and Page 4 may be individually swapped into the address space originally occupied by Page 1 (the swappable page area). In the preferred embodiment, Page 2 is held static and thus is not used as a swap area. Each of the swappable pages, Page 1, Page 3, and Page 4, contain processing logic called swapping logic used during the swapping or paging operation. The swapping logic operates in conjunction with paging hardware to effect the swapping of pages into the swappable page area. The high order processor address lines are input by a page decoder. The page decoder is used to modify the address actually presented to the non-volatile memory device. A page register provides a means by which the processor may select a page in non-volatile memory. In an alternative embodiment of the present invention, several different forms of configuration or identification information may be stored in a page of non-volatile memory.

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Aloha, OR, United States of America

Douglas L Gabel