United Technologies Corporation

Cadence Design Systems, Inc.

Avago Technologies General IP (singapore) Pte. Ltd.

Douglas L Anneser

Barry Jon Male

Martin C Shipley

Martha Johnson

Robert Chizmadia

Thomas E Mitchell

James M Roucis

Andrew M Weilert

A method for detecting and reporting changes in functional features of a simulation model caused by a software revision is disclosed. In one aspect, the method is independent of simulation model architecture. One performs regression testing with a plurality of feature-specific modules. The feature-specific modules are configured to generate a first set of information with the simulation model and compare the first set of information to a second set of corresponding information from the simulation model. In the above-described testing, the first set of information postdates the software revision and the second set of information predates the software revision.

Regression test modules for detecting and reporting changes in process design kits

A transformer-based electrical circuit that isolates a low voltage level input control signal from a power switching device, such a MOSFET, is disclosed. The circuit includes a pair of complementary dual bipolar transistor configurations connected to the secondary winding of a pulse transformer. The low voltage input signal is connected to the primary winding of the transformer. A pair of resistor network transistor drivers connect to corresponding bipolar transistors, whose outputs connect to the gate terminal of the MOSFET. The drivers are also connected to the complementary transistor pairs. A resistive feedback network is connected between the gate terminal of the MOSFET and the complimentary transistor pairs. The feedback network latches the selected drive voltage to the gate of the MOSFET, thereby keeping it on or off irrespective of the fact that the pulse transformer may have saturated.

Isolated MOSFET gate drive

A linear, bipolar-type application-specific integrated circuit includes a silicon substrate having a plurality of columns of device primitives or cells. Each cell comprises a plurality of identical NPN and PNP transistors flanking a centrally-located capacitor. Each transistor has dual emitters, bases and collectors. Open field areas are reserved on the silicon substrate on the sides of the columns of cells. Formed in these open field areas are precise thin film silicon chromium resistors. Power planes are also routed in these open field areas. A ground plane is routed in the vicinity of the centrally-located capacitor. Standard analog circuits are personalized using two layers of metallization interconnects.

Array architecture with enhanced routing for linear asics

The present invention relates to a non-contact current injection apparatus and a method for using the same with linear integrated bipolar circuits. The current injection apparatus has two modes: a calibration mode and an injection mode. The apparatus includes an illumination source for emitting photons toward an electronic component at a desired site for inducing a current in the electronic component. The apparatus further includes a control loop for generating a voltage control signal which causes the illumination source to illuminate to a desired level and a feedback loop which monitors the current induced in the electronic component and compares it or some other end effect to a desired current or end effect. The apparatus also includes a storage device for retaining information about the calibration sequence. The method for using the apparatus broadly comprises calibrating the apparatus using a test array having a series of calibration sites with a target at each site, providing an intensity control signal to the illumination source, illuminating a target at one of the calibration sites, and monitoring the end effect generated in the target by the photon emissions.

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Hollis, NH, United States of America

Douglas L Anneser