Fairchild Semiconductor Corporation

Douglas Joseph Lange

Joseph Andrew Yedinak

Dwayne S Reichl

Bernard J Czeck

Jack Edward Wojslawowicz

Robert Baran

Gary M Dolny

Praveen Muraleedharan Shenoy

Mark L Rinehimer

Sampat Shekhawat

Jon Gladish

An integrated circuit includes a die having a device layer. An insulating layer is disposed over the device layer. A die street defines the outermost bounds of the die. A voltage divider network including a plurality of resistive elements derives a plurality of predetermined bias voltages. A field plate termination includes a plurality of field plates disposed on the oxide layer and are laterally spaced apart relative to each other and relative to the die street. Each of the plurality of field plates is electrically connected to a corresponding bias voltage. The bias voltage applied to a given field plate is determined by and increases with the proximity of that field plate relative to the die street.

Voltage divider field plate termination with unequal fixed biasing

An integrated circuit die includes an active area having source dopants and contacts. An active area metal layer overlies the active area. A sense area is disposed on the die. A sense area metal layer overlies the sense area. A plurality of polysilicon gate stripes, polysilicon openings, and body stripes are disposed on the die, and extend in a continuous and uninterrupted manner from the active area into the sense area. A first region from which source dopants and contacts have been excluded surrounds a periphery of the sense area. An etched region is disposed over the first region, thereby separating and electrically isolating the sense area metal layer from the active area metal layer.

Method of isolating the current sense on power devices while maintaining a continuous stripe cell

A quick punch-through integrated gate bipolar transistor (IGBT) includes a drift region and a gate. The drift region has a drift region dopant concentration and a drift region thickness. The gate has a gate capacitance. The drift region dopant concentration, drift region thickness and gate capacitance are adjusted dependent at least in part upon the PNP gain of the IGBT to maintain the potential difference between the gate and emitter at a level greater than the IGBT threshold voltage when the collector voltage reaches the bus voltage. This insures that the hole carrier concentration remains approximately equal to or greater than the drift region dopant concentration when the depletion layer punches through to the buffer region during the turn-off delay. Thus, the collector voltage overshoot and the rate of change of voltage and current are controlled, and electromagnetic interference is reduced, during turn off.

Quick punch through IGBT having gate-controllable DI/DT and reduced EMI during inductive turn off

An IGBT has striped cell with source stripes continuous or segmented along the length of the base stripe The opposite stripes are periodically connected together by the N&plus; contact regions to provide channel resistance along the width of the source stripes . For continuous stripes the resistance between two sequential contact areas is greatest in the middle and current concentrates near the source contact regions The wider the spacing between the contacts the larger the resistive drop to the midpoint between two N&plus; contacts

IGBT with channel resistors

An IGBT has a thick buffer region with increased doping to improve self-clamped inductive switching and device manufacture. A planar or trench gate IGBT has a buffer layer more than 25 microns thick. The buffer layer is doped high enough so that its carriers are more numerous than minority carriers, particularly at the transition between the N buffer & N drift region.

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Mountain Top, PA, United States of America

Douglas Joseph Lange