Micron Technology Incorporated

Hewlett-packard Development Company, L.P.

Hewlett-packard Company

Other

Douglas John Cutter

Kurt D Beigel

Fan Ho

Manny K Ma

James E Miller, Jr

Eric T Stubbs

Daryl L Habersetzer

Gordon D Roberts

Jeffrey D Bruce

Patrick J Mullarkey

Brett M Debenham

Kim M Pierce

Dien S Luong

Adrian E Ong

Christophe Pierrat

Reid James Riedlinger

Todd A Merritt

Jeffrey P Wright

Michael Amiel Shore

Hua Zheng

Samuel D Naffziger

Dean A Mulla

Steven Frederick Liepe

Thomas Grutkowski

Daming Jin

Rich McGowen, Ii

Christopher Craig Seib

Kurt D Biegel

A system for preventing processor errors in accordance with one exemplary embodiment of the present disclosure has a processor core, a patch, and a controller. The patch configures the processor core to detect occurrences of an event indicative of an imminent error in the processor core. The controller is configured to adjust, in response to a detection of an occurrence of the event by the processor core, a clock signal or a power signal provided to the processor core such that the imminent error is prevented.

System and method for preventing processor errors

A processor comprises a processor core and a controller. The processor core has an execution unit configured to execute instructions and to attempt to perform at least one operation in executing one of the instructions. The processor core is configured to detect a processor error associated with the at least one operation. The controller is configured to change an operating point of the processor core in response to a detection of the processor error such that the processor core operates at a new operating point, and the processor core is configured to retry the at least one operation while the processor core is operating at the new operating point.

System and method for adjusting operating points of a processor based on detected processor errors

A processor comprises a chip, a temperature sensing device, a processor core, and a controller. The temperature sensing device, the processor core, and the controller are integrated on the chip. The controller is configured to set, based on the temperature sensing device, the processor core to a plurality of specified operating points to enable testing of the specified operating points. Each of the operating points is defined by a different temperature and frequency combination, and the processor core is configured to run a set of test codes at each of the operating points.

System and method for testing a processor

As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

Method and device for testing a sense amp

Method and apparatus are disclosed for checking the resistance of antifuse elements in an integrated circuit. A voltage based on the resistance of an antifuse element is compared to a voltage based on a known resistance, and an output signal is generated whose binary value indicates whether the resistance of the antifuse element is higher or lower than the known value of resistance. The method and apparatus are useful in verifying the programming of antifuse elements.

Method and apparatus for checking the resistance of programmable elements

As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

Circuit and method for voltage regulation in a semiconductor device

The cancellation of a redundant element of an integrated circuit with a cancel bank is disclosed. In one embodiment, a fuse or antifuse bank is coupled to the redundant element and permanently programmed to respond to the address of a defective primary element. If the redundant element is found to be defective, the fuse or antifuse bank is canceled, and a result the redundant element is also canceled. A cancel line of the fuse or antifuse bank, along with the cancel line of each of a plurality of other fuse or antifuse banks, is coupled to a cancel bank. The cancel bank comprises a multiplexer and a plurality of cancel antifuses less in number than the number of fuse or antifuse banks. The cancel antifuses are selectively enabled such that the fuse or antifuse bank coupled to the defective redundant element may be canceled.

Cancellation of redundant elements with a cancel bank

The inventive control logic provides the selection signals for a bi-endian rotator MUX. The logic determines the starting point for the data transfer by determining which input register byte is going to Byte of the output register. The control logic passes the starting point to single decoder. The decoded value is then sent to a plurality of MUXs, one for each of the output register bytes. Each of the MUXs is prewired to receive a portion of bits of the decoded value, and the portion is arranged in a particular order. The MUXs then send their respective outputs to the rotator MUX as selection control signals.

Distributed MUX scheme for bi-endian rotator circuit

A programmable circuit includes a first node and provides a programmed signal based on the state of the first node. A first anti-fuse has a programmed state and an unprogrammed state and couples the first node to a first power supply when in the programmed state and decouples the first node from the first power supply when in the unprogrammed state. A second anti-fuse has a programmed state and an unprogrammed state and couples the first node to a second power supply when in the programmed state and decouples the first node from the second power supply when in the unprogrammed state. The state of the programmed signal can be used to replace a primary circuit element of an integrated circuit with a redundant circuit element.

Low current redundancy anti-fuse method and apparatus

An electronically programmed mask is connected to an electronic device, such as a processor. In operation, a mask design is first entered into the processor. The processor controls a display of an image on the electronically programmed mask, wherein the display replicates conventional type masks. The electronically programmed mask is designed such that the display presented on its screen provides optical contrast and characteristics that are easily changed or reprogrammed by the processor. Electronically controlled masks provide the same patterns as mechanical type masks without requiring rigid, permanent type structures to form a desired pattern.

Electrically programmable photolithography mask

A method and apparatus for forming a junctionless antifuse semiconductor structure comprises forming an antifuse in non-active areas of a semiconductor wafer. In one embodiment, the antifuse is formed over a polysilicon layer, which is coupled to a field oxide layer. In a further embodiment, the polysilicon layer comprises a bottom conductor layer in the antifuse. In another embodiment, a refractory metal silicide layer is formed between the polysilicon layer and the antifuse. In yet a further embodiment, the refractory metal silicide layer comprises the bottom conductor layer in the antifuse.

Junctionless antifuses and systems containing junctionless antifuses

Disclosed are methods and apparatus for finding an element meeting a predetermined condition among an ordered set of N elements. The method subdivides the ordered set of N elements into M subsets, wherein 1<M<N. A particular one of the M subsets contains K elements. The method determines if the particular subset contains an element meeting the predetermined condition. The method also identifies which of the K elements in the particular subset is the first element meeting the predetermined condition.

Method and apparatus for finding a first element

Circuitry for detecting snoop hits during the propagation and storage delay when transmitting a victim address to a bus cluster in a multiprocessor system. The circuitry includes stages for detecting the snoop hits during each cycle of the propagation delay. Each stage includes logic gates for comparing the wordline address with a snoop hit and for outputting a snoop hit signal upon detection of a snoop hit relating to the snoop address.

Growing community of inventors

Fort Collins, CO, United States of America

Douglas John Cutter